Dr. Wei Qin's Resume Page

	Wei Qin
	Assistant Professor Dept. of Electrical & Computer Engineering Boston University 8 Saint Mary's Street Boston, MA 02215 Phone: (617)358-3641 Email: wqin@bu.edu
	Research Interests Education Professional Experience Professional Activities Award Funding Publications Dissertation Software Release
	RESEARCH INTERESTS Design tools and methods for embedded systems and embedded processors Design language for electronic systems
	EDUCATION Ph.D in Electrical Engineering (2004) Princeton University, Princeton, NJ. Thesis: Modeling and Description of Embedded Processors for the Development of Software Tools M.Sc. in Electronics Engineering (1999) Fudan University, Shanghai, China. Thesis: A Novel Sigma-Delta Analog-to-Digital Conversion Architecture (in Chinese) B.Sc. in Electronics Engineering (1996) Fudan University, Shanghai, China.
	PROFESSIONAL EXPERIENCE Assistant Professor, ECE Department, Boston University, 9/2004 — present Graduate Research Assistant, EE Department, Princeton university, 9/1999 — 8/2004 Summer Intern, Improv Systems Inc., 7/2001 — 8/2001 Graduate Teaching Assistant, EE Department, Princeton University, 9/1999 — 6/2000 Graduate Research Assistant, EE Department, Fudan University, 9/1996 — 6/1999 Graduate Teaching Assistant, EE Department, Fudan University, 9/1997 — 1/1998
	PROFESSIONAL ACTIVITIES Conference Co-chair: BARC 2007 Conference Publicity-chair: ASAP 2009 Conference Program Committee: DATE 2003, SoC 2007/2008, NCUS 2007/2008, AINA 2008, GLSVLSI 2009, ISVLSI 2009 Reviewer Assignment: DAC, ICCD, DATE, GLSVLSI IEEE TPDSSI, IEEE TVLSI ACM TODAES, ACM TACO, ACM TCES MICRO Invited Talks: Lyra: A Concurrent Model to Bridge Transaction Level Modeling and RTL Implementation University of Rhode Island, Kingston, RI, Feb 25, 2009 Rendezvous Finite State Machine - Where Where TLM meets RTL Freescale Semiconductor, Herzlia, IL, July 3, 2008 An ADL for Functional Specification of IA32 Intel DTS Annual Symposium, Haifa, IL, June 30, 2008 MADL: An Architecture Description Languages for Software Tool-chain Synthesis Intel Corp, Haifa, IL, Nov. 23, 2006 A Survey of Architecture Description Languages Intel Corp, Haifa, IL, Nov. 22, 2006 RFSM: A Formalism for Modeling Complex Digital Systems Freescale Semiconductors, Austin, TX, Sept. 14, 2006 Constructing Portable and Retargetable Compiled Instruction-Set Simulators Virginia Polytechnic Institute and State University, Blacksburg, VA, March 3, 2006 A Study of Architecture Description Languages from a Model-based Perspective Shanghai Jiaotong University, Shanghai, China, Dec. 23, 2005 A Study of Architecture Description Languages from a Model-based Perspective MTV 2005, Austin, TX, Nov. 3, 2005 Description of Embedded Processors for the Synthesis of Software Tools EDCEP 2004, Washington DC, Sept. 25, 2004 SoC Modeling based on a Formal Concurrency Model IBM T. J. Watson Research Center, May 12, 2004
	AWARD 2005/2006 ECE Faculty Teaching Award
	RESEARCH FUNDING Rendezvous Finite State Machine: where TLM meets RTL, $60K/year, SRC/Freescale, 2007-2010 Automatic functional test generation from ADL, $90K, Intel, 2006-2009
	PUBLICATIONS Vyas Venkataraman, Di Wang, Atabak Mahram, Wei Qin, Mrinal Bose, and Jayanta Bhadra, Synthesis Oriented Scheduling of Multiparty Rendezvous in Transaction Level Models, IEEE CS Annual Symposium on VLSI, May, 2009 (to appear). Di Wang, Vyas Venkataraman, Zhen Wang, Wei Qin, Hangsheng Wang, Mrinal Bose, and Jayanta Bhadra, Accelerating Multi-party Scheduling for Transaction-level Modeling, ACM/IEEE Great Lakes Symposium on VLSI, May, 2009 (to appear). W. Qin, S. Malik, MADL: An ADL based on a Formal and Flexible Concurrency Model, in Processor Description Languages: Applications and Methodologies, Morgan Kaufman Publishers, P. Mishra, N. Dutt, Editors, 2008. W. Qin, A. Ben-Tzur, B. Gutkovich, An ADL for Functional Specification of IA32, IEEE 8th International Workshop on Microprocessor Testing and Verification, Dec. 2007. pdf W. Qin, S. Malik, Architecture Description languages for retargetable compilation, in The Compiler Design Handbook: Optimizations & Machine Code Generation, CRC Press, 2007, Y. N. Srikant and Priti Shankar, Editors, 2nd Edition. Y. Mahajan, C. Chan, A. Bayazit, S. Malik, W. Qin, Verification Driven Formal Architecture and Microarchitecture Modeling, MEMOCODE'07, April, 2007. pdf W. Qin, J. D'Errico, X.Zhu, A New Approach to Constructing Portable Instruction-Set Simulators, Fifth Annual Boston Area Architecture Workshop, January 2007. W. Qin, RFSM: A Rendezvous of TLM and RTL, IEEE 7th International Workshop on Microprocessor Testing and Verification, Dec. 2006. W. Qin, J. D'Errico, X. Zhu, A Multiprocessing Approach to Accelerate Retargetable and Portable Dynamic-compiled Instruction-set Simulation, International Conference on Hardware/Software Codesign and System Synthesis, November 2006. pdf B. C. Lai, P. Schaumont, W. Qin, I. Verbauwhede, Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), September, 2006. pdf X. Zhu, W. Qin, S. Malik, Modeling Operation and Microarchitecture Concurrency for Communication Architectures with Application to Retargetable Simulation, IEEE Transactions on Very Large Scale Integration Systems, Vol. 7, No. 14, July 2006. pdf X. Zhu, W. Qin, Modeling a Fault-Tolerant Multiprocessor SoC with Run-time Fault Recovery, 43th ACM Design Automation Conference, July 2006. pdf J. D'Errico, W. Qin, Constructing Portable Compiled Instruction-set Simulators -- An ADL-driven Approach, IEEE/ACM Design Automation and Test in Europe, March 2006. pdf W. Qin, S. Malik, A Study of Architecture Description Languages from a Model-based Perspective (invited), IEEE 6th International Workshop on Microprocessor Testing and Verification, Nov. 2005. pdf W. Qin, B. Hu, A Technique to Exploit Memory Locality for Fast Instruction Set Simulation, 6th International Conference on ASIC, Oct. 2005. pdf B.C. Lai, P. Schaumont, W. Qin, I. Verbauwhede, Energy and Performance Analysis of Mapping Parallel Multithreaded Tasks for An On-Chip Multi-Processor System, IEEE Internation Conference on Computer Design, Oct. 2005. pdf P. Schaumont, B.C. Lai, W. Qin, I. Verbauwhede, Cooperative multithreading on embedded multiprocessor architectures enables energy-scalable design, 42th ACM Design Automation Conference, June 2005. pdf X.Zhu, W.Qin, S.Malik, Modeling Operation and Microarchitecture Concurrency for Communication Architectures with Application to Retargetable Simulation, IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, Sept. 2004. pdf W.Qin, S.Rajagopalan, S.Malik, A Formal Concurrency Model Based Architecture Description Language for Synthesis of Software Development Tools, ACM 2004 Conference on Languages, Compilers, and Tools for Embedded Systems, June 2004, pp. 47-56. pdf W. Qin, S. Malik. Automated Synthesis of Efficient Binary Decoders for Retargetable Software Toolkits, 40th ACM Design Automation Conference, June 2003, pp. 764-769. pdf W. Qin, S. Malik. Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation, IEEE/ACM Design Automation and Test in Europe, March 2003, pp. 556-561. pdf W. Qin, S. Rajagopalan, M. Vachharajani, H. Wang, X. Zhu, D. August, K. Keutzer, S. Malik, L. Peh. Design Tools for Application Specific Embedded Processors (invited). 2nd ACM International Conference on Embedded Software, October, 2002. W. Qin, S. Malik, Architecture Description languages for retargetable compilation, in The Compiler Design Handbook: Optimizations & Machine Code Generation, CRC Press, 2002, Y. N. Srikant and Priti Shankar, Editors. X. Wang, W. Qin, X. Ling, Cascaded parallel oversampling sigma-delta modulators, IEEE Trans. Circuit and Systems II: Analog and Digital Signal Processing, vol.47, no.2, Feb. 2000, pp. 156-161. pdf X. Ling, W.Qin, B. Hu, Log-Domain Integrator and Its Applications (in Chinese), Acta Electronica Sinica, vol.28, no.2, pp. 46-48, Feb. 2000. W. Qin, B. Hu, X. Ling, Sigma-Delta ADC with reduced sample rate multibit quantizer, IEEE Trans. Circuit and Systems II: Analog and Digital Signal Processing, vol.46, no.6, June, 1999, pp. 824-828. pdf W. Qin, X. Ling, B. Hu, G. Ruan, Pvreg: a generic behavioral model of linear voltage regulators (in Chinese), Acta Electronica Sinica, vol.27, no.11, pp130-132, Nov. 1999. X. Ling, W. Qin, B. Hu, CMOS Current Controlled Conveyor and Its Applications (in Chinese), Acta Electronica Sinica, vol.27, no.8, Aug. 1999.
	DISSERTATION W. Qin, Modeling and Description of Embedded Processors for the Development of Software Tools, Ph.D. Dissertation, Princeton University, Nov. 2004. pdf
	SOFTWARE RELEASE SimIt-ARM, 2002 — present http://simit-arm.sourceforge.net Open-source instruction-set simulator and microarchitecture simulator for StrongARM. MADLC, 2004 — present http://people.bu.edu/wqin/madl-1.0.1.tar.gz MADL compiler and simulator generator. SimIt-MIPS, 2005 — present http://simit-mips.sourceforge.net Open-source instruction-set simulator for MIPS32.
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