Welcome to my (temporary) homepage



Who Am I : A graduate student in the ECE Department at Boston University

What Do I do : I currently work on High Level Modeling and Synthesis under Prof Wei Qin and Prof Alexander Taubin

What Interests me : High Level Synthesis, Electronic System Level design, Electronic Design Automation, Asynchronous Circuits

Publications:
  1. "Asynchronous balanced gates tolerant to interconnect variability", K. Kulikowski, V. Venkataraman ,Z. Wang, A. Taubin, M. Karpovsky, ISCAS 2008
  2. "Power Balanced Gates Insensitive to Routing Capacitance Mismatch", K. Kulikowski, V. Venkataraman ,Z. Wang, A. Taubin, M. Karpovsky, DATE 2008 Awarded Best Paper for DATE 2008
  3. "Accelerating Multi-party Scheduling for Transaction-level Modeling", D. Wang, V. Venkataraman, Z. Wang, W. Qin, M. Bose, J. Bhadra, accepted to GLSVLSI 2009
  4. "Synthesis-oriented scheduling of multiparty rendezvous in Transaction Level Models", V. Venkataraman, D. Wang, A. Mahram, W. Qin, M. Bose, J. Bhadra, accepted to ISVLSI 2009


Contact Information : Vyas Venkataraman
Boston University, Electrical and Computer Engineering Dept
8 St Mary St. Boston MA 02215
email : vyas@bu.edu