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Books (in reverse chronological order):
1.
A.
Taubin, J. Cortadella, L. Lavagno,
A. Kondratyev and A. Peeters. Design Automation of Real-Life
Asynchronous Devices and Systems. Foundations and Trends® in Electronic
Design Automation – Vol.2, No. 1, September, 2007, pp. 1-133.
2. M. A. Kishinevsky, A. Y. Kondratyev, A.
R. Taubin, and V. I. Varshavsky. Concurrent
Hardware. The Theory and Practice of Self-Timed Design. John Wiley and
Sons Ltd., 1994
3. V.I. Varshavsky, M. A. Kishinevsky, V. B. Marakhovsky, V. A. Peschansky, L. Y.
Rosenblum, A. R. Taubin, and B. S. Tzirlin. Self-timed Control of
Concurrent Processes. Kluwer Academic Publishers, 1990.
Book chapters (in reverse chronological order):
4.
K.J. Kulikowski, A. Smirnov and A. Taubin,
Automated Design of Cryptographic Devices Resistant to Multiple
Side-Channel Attacks, in Cryptographic Hardware and Embedded
Systems - CHES 2006, Springer, September, 2006. pp. 399-413
5.
Konrad J.
Kulikowski, Mark G. Karpovsky, Alexander Taubin, DPA on Faulty
Cryptographic Hardware and Countermeasures, in Fault Diagnostic
and Tolerance in Cryptography, Springer, September 2006 pp. 211-222.
6.
Konrad J. Kulikowski, Mark G. Karpovsky, Alexander
Taubin, Fault Attack Resistant Cryptographic Hardware with Attack
Independent Uniform Error Detection, in
Fault Diagnostic and Tolerance
in Cryptography, Springer, September 2006, pp
185-195.
7.
M.
Kishinevsky, J. Cortadella, A. Kondratyev, L. Lavagno, A. Taubin, and A.
Yakovlev. Coupling asynchrony and interrupts: Place chart nets and their
synthesis. In Application and Theory of Petri Nets, Springer, 1997,
pp. 328-347
8.
A.
Kondratyev, M. Kishinevsky, A. Taubin, and S. Ten. A structural approach
for the analysis of Petri nets by reduced unfoldings. In Application and
Theory of Petri Nets, Springer, 1996. pp. 346-365
Journal papers (in reverse chronological order):
9. Tejpal
Singh, Alexander Taubin, A Highly Scalable GALS Crossbar Using Token Ring
Arbitration, IEEE Design & Test, September-October 2007, pp.464-472.
10.
Konrad J. Kulikowski, Mark G. Karpovsky,
Alexander Taubin, Robust Codes and Robust, Fault Tolerant Architectures of
the Advanced Encryption Standard, Journal of Systems Architecture, Volume
53, Issues 2-3 (February-March), 2007, pp.139-149.
11. M. Karpovsky and A. Taubin. New
Class of Nonlinear Systematic Error Detecting Codes. IEEE Transactions
on Information Theory, Vol.
50, No.8 (August), 2004, pp.1818-1820.
12. J.
Cortadella, A. Kondratyev, L. Lavagno, A. Taubin and Y. Watanabe, Quasi-static Scheduling for Concurrent
Architectures, Fundamenta Informaticae, Vol 62, Number 2, July 2004, pp
171-196.
13.
J. Cortadella, M. Kishinevsky, S.M. Burns,
A. Kondratyev, L. Lavagno, K.S. Stevens, A. Taubin and A. Yakovlev, Lazy transition
systems and asynchronous circuit synthesis with relative timing assumptions.
IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems, Vol. 21, No. 2, Feb. 2002,
pp. 109-130.
14.
M. Kishinevsky,
A. Kondratyev, L. Lavagno, A. Saldanha, and A. Taubin. Partial scan delay
fault testing of asynchronous circuits. IEEE Transactions on
Computer-Aided Design, 17(11):1184-1199, 1998.
15.
A. Kondratyev, M. Kishinevsky, A. Taubin, J.
Cortadella, and L. Lavagno. The use of Petri nets for the design and
verification of asynchronous circuits and systems. Journal of Circuits,
Systems, and Computers, 8(1):67-118, 1998.
16.
A. Taubin, M. Kishinevsky, and A.
Kondratyev. Deadlock prevention using Petri nets
and their unfoldings. International Journal of Advanced Manufacturing
Technology, 14(10):750-759,1998.
17.
A.
Kondratyev, M. Kishinevsky, A. Taubin, and S. Ten. Analysis of Petri nets
by ordering relations in reduced unfoldings. Formal Methods in System
Design, 12(1):5-38, 1998.
18.
M.A.
Kishinevsky, A.Yu. Kondratyev, A.R. Taubin, and V.I. Varshavsky. Analysis
and identification of speed-independent circuits on an event model. Formal
Methods in System Design, 4(1):33-75, 1994.
19.
M.
Kishinevsky, A.Yu. Kondratyev, and A.R. Taubin. Specification and analysis
of self-timed circuits. Journal of VLSI Signal Processing, 7(1-2):117-135,
1994.
20.
V.I.
Varshavsky, M. A. Kishinevsky, A. Y. Kondratyev, L. Y. Rosenblum, and A. R.
Taubin. Models for specification and analysis of processes in asynchronous
circuits. Izvestiia Akademii nauk SSSR, Tekhnicheskaya Kibernetika, pages
171-190, 1988. English translation: Soviet Journal of Computer and Systems
Sciences.
21.
V.
Varshavsky, M. Kishinevsky, A. Taubin, and L. Rosenblum. Autonomous device
fault checking. Elektronnoe Modelirovanie (USSR), (2):64-69,101,
October 1985. (English translation in: Electronic Modeling (UK)).
22.
V.
I. Varshavsky, M. A. Kishinevsky, A. Taubin, and B. Tsilrlin. Asynchronous
logic circuits analysis. Part I: the reachability problem and
speed-independent circuits. Izvestiia Akademii nauk SSSR, Tekhnicheskaya
Kibernetika, (3):137-149, 1982. English translation: Soviet Journal of
Computer and Systems Sciences.
23.
V.
I. Varshavsky, M. A. Kishinevsky, A. Taubin, and B. Tsilrlin. Asynchronous
logic circuits analysis. Part II: reachability of working states and
influence of wire delays. Izvestiia Akademii nauk SSSR, Tekhnicheskaya
Kibernetika, (4):84-97, 1982. English translation: Soviet Journal of
Computer and Systems Sciences.
24.
M. Kishinevsky,
A. Taubin, and B. Tsirlin. Petri nets and switching circuits analysis. Cybernetics,
(4):114-117, 1982. Translated into English.
25.
V.
Varshavsky, L. Rosenblum, and A. Taubin. Totally self-checking asynchronous
combinational circuits and the indication property. Avtomatika i
Telemekhanika (USSR),
(5):138-146, October 1982. (English translation in: Automation and
Remote Control (USA)).
Conference papers (in reverse chronological order):
26. A.
Smirnov, A. Taubin, Heuristic based
throughput analysis and optimization of asynchronous pipelines, Proc. 15th IEEE International Symposium on
Advanced Research in Asynchronous Circuits and Systems, May 2009 (accepted).
27.
K. Kulikowski, M. Karpovsky, Z. Wang, A. Kulikowski,
and A. Taubin, Concurrent Fault Detection for Secure QDI Asynchronous
Circuits, 2nd Workshop on Dependable & Secure Nanocomputing. In
conjunction with the 38th Annual IEEE/IFIP International Conference on
Dependable Systems and Networks, June 2008
28.
K. Kulikowski, V. Venkataraman, Z. Wang, M. Karpovsky and A. Taubin, Asynchronous
Balanced Gates Tolerant to Interconnect Variability, ISCAS, 2008 IEEE International Symposium on Circuits
and Systems, May 2008
29.
K. Kulikowski, V. Venkataraman, Z. Wang
and A. Taubin, Power Balanced Gates
Insensitive to Routing Capacitance Mismatch, The 11th
Design, Automation and Test in Europe (DATE), pp.
1280-1286, March 2008. (Best paper award – out of 198
accepted papers that were selected from 839 submitted).
30.
A. Smirnov
and A. Taubin, Synthesizing Asynchronous Micropipelines with
Design Compiler, SNUG’06, September, 2006.
31.
T. Singh
and A. Taubin, A GALS
Solution Based on Highly Scalable, Low Latency, Crossbar Using Token Ring
Arbitration, The 49th IEEE International Midwest Symposium on Circuits and
Systems. August , 2006.
32.
K.J.
Kulikowski, M.G. Karpovsky and A.
Taubin, Power Attacks on Secure Hardware Based on Early Propagation
of Data, 12th IEEE International
On-Line Testing Symposium. July, 2006
33.
A.
Smirnov, M. Karpovsky and A.
Taubin On Automatic Synthesis of Data Dependent
Micropipelines The 15th
International Workshop on Logic and Synthesis, June 2006.
34. K.
J. Kulikowski, M. Karpovsky and
A. Taubin , "Robust Codes for Fault Attack Resistant Cryptographic Hardware", Workshop on Fault Diagnosis and Tolerance
in Cryptography 2005 (FTDC05), September 2005.
35. A.
Smirnov, M. Karpovsky and A. Taubin. An Automated Fine-Grain Pipelining
Using Domino Style Asynchronous Library, ACSD 2005: Fifth International
Conference on Application of Concurrency to System Design, June 2005, pp.
68-76.
36.
K. Kulikowski, M. Karpovsky, and A. Taubin. Memories
with Robust Self Error Detection and Correction Invariant to Error
Distributions, European Test Symposium, May
2005.
37.
K.Kulikowski,
M.Su, A.Smirnov, A.Taubin, M.G.Karpovsky, and D.MacDonald, Delay Insensitive Encoding and Power Analysis:
A Balancing Act, Proc.
11th IEEE International Symposium on Advanced
Research in Asynchronous Circuits and Systems, March
2005, pp.116-125.
38. M.
Karpovsky, K. Kulikowski and A. Taubin. Differential Fault Analysis Attack
Resistant Architectures for the Advanced Encryption Standard. CARDIS 04: Sixth smart Card
Research and Advanced Application IFIP Conference, Proc. World
Computing Congress, August, 2004, pp.177-192.
39.
M. Karpovsky, K. Kulikowski and A. Taubin. Robust
Protection against Fault-Injection Attacks of Smart Cards Implementing the
Advanced Encryption Standard. DSN04: The International Conference on Dependable Systems and Networks,
June, 2004, p.93 – 101.
40.
Smirnov A., Taubin A., Karpovsky M. and Rozenblyum
L. Gate Transfer Level Synthesis as an Automated Approach to
Fine-Grain Pipelining in Workshop on Token Based Computing (ToBaCo). June 22, 2004. Bologna, Italy, p.67-77
41.
Smirnov A., Taubin A., and Karpovsky M. Automated
Pipelining in ASIC Synthesis Methodology: Gate Transfer Level. in IWLS
2004 Thirteenth International Workshop on Logic and Synthesis. June 2-4, 2004. Temecula, California,
USA,
p.416-423
42.
A.
Taubin and M. Karpovsky Devices
Resistant to Attacks. Design Methodology. 2002 Fall IEEE Conference on
Technologies for Homeland Security, November 13-14, 2002
43.
A.Taubin, K. Fant and J. McCardle. Design of
Delay-Insensitive Three Dimension Pipeline Array Multiplier for Image
Processing, Proceedings, 2002 IEEE International Conference on Computer
Design: VLSI in Computers and Processors. ICCD’2002, p.p.104-111
44.
A. Kondratyev, L. Neukom, O. Roig, A. Taubin
and K. Fant Checking Delay-Insensitivity: 104 Gates and
Beyond. In International
Symposium on Advanced Research in Asynchronous Circuits and Systems,
April 2002, p. 149-157.
45.
Michiel Ligthart, Karl Fant, Ross Smith,
Alexander Taubin, Alex Kondratyev
Asynchronous Design Using Commercial HDL Synthesis Tools. In International Symposium on Advanced
Research in Asynchronous Circuits and Systems, April 2000.
46.
A. Taubin, A. Kondratyev, J. Cortadella, and
L. Lavagno. Behavioral
transformations to increase the noise immunity of asynchronous
specifications. In International Symposium on Advanced Research in
Asynchronous Circuits and Systems, pages 36-47, April 1999.
47. A. Kondratyev, J. Cortadella, M.
Kishinevsky, L. Lavagno, A. Taubin, and A. Yakovlev. Lazy transition
systems: application to timing optimization of asynchronous circuits. In Proceedings
of the International Conference on Computer-Aided Design, pages
324-331, November 1998.
48.
A.
Kondratyev, J. Cortadella, M. Kishinevsky, L. Lavagno, A.Taubin, and A.
Yakovlev. Identifying state coding conflicts in asynchronous system
specifications using Petri net unfoldings. In Proc. of the International
Conference on Application of Concurrency to System Design (CSD '98), pages
152-163, Fukushima, Japan, March 1998.
49.
A. Taubin, A. Kondratyev, J. Cortadella, and
L. Lavagno. Crosstalk noise
avoidance in asynchronous circuits. In Proceedings of the ACM/IEEE
International Workshop on Timing Issues in the Specification and Synthesis
of Digital Systems (TAU), pages 123-128, March 1999.
50.
A.
Taubin, A. Kondratyev, and M. Kishinevsky. Applications of Petri nets
unfoldings to asynchronous design. In 1997 IEEE International Conference
on Systems, Man, and Cybernetics, volume 5, pages 4279-4284, Orlando, Florida,
October 1997.
51.
Michael
Kishinevsky, Alex Kondratyev,
Luciano Lavagno, Alex Saldanha, and Alexander Taubin. Partial scan delay
fault testing of asynchronous circuits. In Proceedings of the
International Conference on Computer-Aided Design, pages 728-735,
November 1997.
52.
Michael
Kishinevsky, Alex Kondratyev, Luciano
Lavagno, Alex Saldanha, and Alexander Taubin. Delay fault testing of
asynchronous sequential circuits. In Proc. of IWLS '97: International
Workshop on Logic Synthesis, May 1997.
53.
A.
Taubin, A. Kondratyev, M. Kishinevsky, and S. Ten. Deadlock prevention
using Petri net unfoldings. In Computational Engineering in Systems
Applications. CESA '96 IMACS/IEEE/SMC Multiconference, pages 426-431,
July 1996.
54.
A.
Taubin, A. Kondratyev, and M. Kishinevsky. Deadlock prevention by Petri
nets transformations. In Proc. of IEICE Concurrent Systems Technology
Conference, CST-96, Aizu-Wakamatsu,
Japan, May
1996.
55.
S.
Ten, A. Kondratyev, M. Kishinevsky, and A. Taubin. Software tool offering
Petri net unfolding construction. In Proceedings of the 16th
International Conference on Application and Theory of Petri Nets. Tool
presentation, Torino,
Italy, June
1995.
56.
A.
Kondratyev, A. Taubin, V. Varshavsky, M. Kishinevsky, and E.E. Pissaloux.
Change diagram: a behavioral model for very speed VLSI circuits/highly
parallel systems. In Proc. Euromicro Workshop on Parallel and
Distributed Processing, pages 220-226, Los Alamitos, California,
January 1994. IEEE Computer Society Press.
57.
A.
Kondratyev and A. Taubin. Verification of speed-independent circuits by STG
unfoldings. In Proceedings of the Symposium on Advanced Research in
Asynchronous Circuits and Systems, pages 64-75, Utah,
USA,
November 1994.
58.
Alex
Kondratyev, Alexander Taubin, and Sergey Ten. Verification of asynchronous
circuits by Petri net unfoldings. In 1994 IEEE Symposium on Emerging
Technologies and Factory Automation, ETFA '94, pages 404-413, November
1994.
59.
A.
Kondratyev, M. Kishinevsky, and A. Taubin. Synthesis method in self-timed
design. Decompositional approach. In IEEE International Conference on
VLSI and CAD, November 1993.
60.
A.
Taubin, M. Kishinevsky, and A. Kondratyev. Self-timed formal design based
on generalized behavioral specification. In Proc. of the International
Int. Workshop on Design Automation ("Russian Workshop-93"), pages
2O-37, Moscow, Russia, July 1993.
61.
M.
A. Kishinevsky, A. Y. Kondratyev, A. R. Taubin, and V. I. Varshavsky. On
self-timed behavior verification. In Proceedings of the A CM/IEEE
International Workshop on Timing Issues in the Specification and Synthesis
of Digital Systems (TAU), 1992.
62.
M.
A. Kishinevsky, A. Y. Kondratyev, A. R. Taubin, and V. I. Varshavsky.
Analysis and identification of self-timed circuits. In Proceedings of
IFIP 2nd Workshop on Designing Correct Circuits, pages 275-287, January 1992.
63.
M.
Kishinevsky, A. Kondratyev, and A. Taubin. Concurrent hardware. One
decomposition approach in self-timed design. In Proc. of the
International Workshop on Design Automation ("Russian
Workshop-92"), pages 61-76, Moscow,
Russia,
June 1992.
64.
M.
A. Kishinevsky, A. Y. Kondratyev, and A. R. Taubin. Formal method for
self-timed design. In Proceedings of the European Design Automation
Conference (EDA C), 1991.
65. M. A. Kishinevsky, A. Y. Kondratyev, L.
Y. Rosenblum, and A. R. Taubin. Models for asynchronous concurrent circuit
processes and its analysis. In Proceedings of the International
Conference on Formal Models for Concurrent Computation, pages 83-92, Novosibirsk, Russia, 1988.
PhD thesis
A. Taubin. Analysis of self-timed circuits. PhD thesis,
Dept. of Computer Science, Leningrad Electrical Engineering Institute,
November 1981. (in Russian).
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