|
CURRENT
POSITION
|
Associate Professor, Electrical and Computer Engineering
Department of Boston
University
|
|
EDUCATION
|
Electrotechnical University of St.Petersburg, Russia.
|
|
|
Department of Computer Science
and Engineering,
|
|
Feb. 1976
|
M. Sc. in Computer Science and
Engineering (with Honors)
|
|
|
Thesis Topic: Design of a
controller for a multiplex I/O channel
|
|
|
|
|
|
Electrotechnical University of St.Petersburg, Russia.
|
|
|
Department of Computer Science
and Engineering,
|
|
Nov. 1981
|
Ph.D. in Computer Science and
Engineering
|
|
|
Advisor: Prof. Victor Varshavsky
|
|
|
Thesis Topic: Analysis of asynchronous (self-timed) circuits
|
|
|
|
|
RESEARCH
|
July 1999 - December 2001 Senior
Scientist Theseus
Logic, Theseus Research
Methods and
algorithms for the automated design (synthesis, optimization and
verification) of asynchronous
circuits and devices. Research in architectural design for
asynchronous microprocessors. Low power techniques. Usage of multi-valued logic for asynchronous
design. Development of the formal methods for the analysis of
delay-insensitivity in combinational circuits (satisfiability based
approach) for verification of large
design.
April 1993 – June 1999
Professor The University of
Aizu, Japan. Department of Computer Hardware,
Research in asynchronous design, formal methods
and algorithms for the automated design of self-timed circuits with reduced
time complexity, testing. Theory of Concurrency, Petri nets, Deadlock
prevention, CAD systems.
|
|
PROFESSIONAL MEMBERSHIPS
|
Senior member of IEEE, IEEE Computer Society
|
|
TEACHING EXPERIENCE
|
Spring 2002 - 2008 “Design of Asynchronous Circuit and Systems” ENG EC751
- Boston University
ENG EC551 – Fall 2003-2008
Advanced Digital Design Automation with Verilog and FPGA;
ENG EC312 - Fall 2003-2008
Computer Organization.
Fall 1997 graduate course: "Synthesis and optimization of
digital circuits. II" The University of Aizu, Japan
Spring 1995, 96, 97, 98 course: "Computer Architecture",
The University of Aizu,
Japan
Fall 1995 and 96, 98 course: "Logic Design", The
University of Aizu, Japan Fall 1995, course: "Computer organization
and FPGA design", The University of Aizu, Japan
|
|
PROFESSIONAL ACTIVITIES
|
Program Co-Chair: Second International Symposium on Advanced
Research in Asynchronous Circuits and Systems (Async96);
Program Co-Chair: 14th International Symposium on Advanced
Research in Asynchronous Circuits and Systems (Async 2008); Tutorial/CAD
Booth Chair: International Conference on Application of Concurrency to
System Design (CSD'98)
Program Committee
Member: ICCAD 2005; International Symposium on Parallel
Algorithm/Architecture Synthesis (pAs'95), International Conference on
Application of Concurrency in System Design (CSD'98), International
Symposiums on Advanced Research in Asynchronous Circuits and Systems (2000,
2003, 2004, 2005, 2006, 2007, 2008, 2009); Workshop on Cryptographic Hardware and Embedded Systems
(CHES) 2007. IEEE Great Lakes Symposium on VLSI (GLSVLSI) 2009.
|
|
