Extended Reading List for SC913 – Summer 2002

 

  1. The Design of CMOS Radio Frequency Integrated Circuits, Thomas H. Lee, Cambridge University Press, 1998.
  2. Analog Integrated Circuit Design, David A. Johns and Ken Martin, Wiley, 1997.
  3. Low-Power CMOS Radio Receivers, Derek Shaeffer and Thomas Lee, Kluwer Academic Publishers, 1999.
  4. Signal Integrity Effects in Custom IC and ASIC Designs, R. Singh, IEEE Press and Wiley & Sons, Nov. 2001.
  5. Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs, X. Aragones, et al., Kluwer Academic Publishers, 1999.
  6. Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits, Verghese, Schmerbeck, and Allstot, Kluwer Academic Publishers, 1995.
  7. “MOS Operational Amplifier Design – A Tutorial Review”, P.R. Gray and R.G. Meyer, IEEE Journal of Solid State Circuits, Vol. SC-17, pp. 969-981, Dec. 1982.
  8. “Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits”, Su, Loinaz, Masui, and Wooley, IEEE Journal of Solid State Circuits, vol. 28, no. 4, pp. 420-430, April 1993.
  9. “Technological Design Considerations for Monolithic MOS Switched-Capacitor Filtering Systems”, Allstot and Black, Proceedings of the IEEE, vol. 71(8), pp. 967-986, 1983.
  10. “Chip Substrate Resistance Modeling Technique for Integrated Circuit Design”, Johnson, Knepper, Marcello, and Wang, IEEE Transactions on Computer-Aided Design, vol. CAD-3, No. 2, pp. 126-134, April 1984.
  11. “A Macromodel Compaction Scheme for the Fast Simulation of Large Linear Mesh Circuits”, Verghese and Allstot, Proceedings of the International Symposium on Circuits and Systems, pp. 1836-1839, May 1995.
  12. “Preventing a NOISEQUAKE”, Ponnapalli, Verghese, Chu, and Coram, IEEE Circuits and Devices Magazine, pp. 19-28, Nov. 2001.
  13. “0.13um 210 GHz Ft SiGe HBTs – Expanding the Horizons of SiGe BiCMOS”, A. Joseph, et al., IEEE ISSCC Digest, paper 11.1, Feb. 2002.
  14. J. Pusl, et al., Microwave Journal, vol. 44, pp. 100-113, 2001 (paper on power amplifier design).
  15. “Addressing substrate coupling in mixed-mode ICs:  Simulation and Power Distribution Synthesis”, Stanisic, Verghese, Allstot, Rutenbar, and Carly, IEEE Journal of Solid-State Circuits, vol. 29, pp. 226-237, Mar. 1994.
  16. “Extraction and Simulation Techniques for Substrate-Coupled Noise in Mixed-Signal Integrated Circuits”, Nishath K. Verghese, PhD Thesis, Carnegie-Mellon University, August 1995.
  17.  “Switching Noise in Mixed-Signal Integrated Circuits”, Tallis Blalack, PhD Thesis, Stanford University, Dec. 1997.
  18. “Principles of Substrate Crosstalk Generation in CMOS Circuits”, Briaire and Krisch, IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems, June 2000.
  19. “A Simple Approach to Modeling Crosstalk in Integrated Circuits”, K. Joardar, IEEE Journal of Solid-State Circuits, Oct. 1994.
  20. “Effects of Substrate Resistances on LNA Performance and a Bondpad Structure for Reducing the Effects in a Silicon Bipolar Technology”, J.T. Colvin, S.S. Bhatia, and K.K. O., IEEE Journal of Solid-State Circuits, Sept. 1999.
  21. “Measurements and Analysis of PLL Jitter Caused by Digital Switching Noise”, P. Larsson, IEEE Journal of Solid-State Circuits, July 2001.
  22. “A Study of Oscillator Jitter Due to Supply and Substrate Noise”, F. Herzel and B. Razavi, IEEE Trans of Circuits and Systems – II: Analog and Digital Signal Processing, Jan. 1999.
  23. “A General Theory of Phase-Noise in Electrical Oscillators”, A. Hajimiri and T.H. Lee, IEEE Journal of Solid-State Circuits, vol. 33, pp. 179-194, Feb. 1998.
  24. “On-Chip Active Guard Ring Band Filters to Suppress Substrate-Coupling Noise in Analog and Digital Mixed-Signal Integrated Circuits”, K. Makie-Fukuda and T. Tsukada, Symposium on VLSI Circuits, Digest of Technical Papers, 1999.
  25. “Complete Mixed-Signal Building Blocks for Single-Chip GSM Baseband Processing”, E. Liu, C. Wong, Q. Shami, S. Mohapatra, R. Landy, P. Sheldon, and G. Woodward, IEEE Custom IC Conference, 1998.
  26. “Low Switching Noise and Load-Adaptive Output Buffer Design Techniques”, S.J. Jou, S.H. Kuo, J.T. Chiu, and T.H. Lin, IEEE Journal of Solid-State Circuits, August 2001.
  27. “Subharmonic Mixers Simplify High Frequency Designs for Personal Communications System”, K.Z. Cai and P. Mambo, Millimeter Wave and Far Infrared Science and Technology, Proceedings, 4th International Conference on, 1996.
  28. “Silicon Substrate Coupling Noise Modeling, Analysis, and Experimental Verification for Mixed-Signal Integrated Circuit Design”, W. Jin, Y. Eo, J.I. Shim, W.R. Eisenstadt, M.Y. Park, and H.K. Yu, RFIC Microwave Symposium, 2001.
  29. IBM SiGe Products Application Note, Bond Pad Devices, IBM Microelectronics, March 2001.
  30. IBM Analog and Mixed Signal Products Application Note, Chip Guard Rings, IBM Microelectronics, August 2001.
  31. IEEE ISSCC Paper, Feb. 2002, CMOS power amp
  32. The Design of a 1.9 GHz 250mW CMOS Power Amplifier for DECT, R. Sekhar Narayanaswami, Report from UC Berkeley.
  33. “Substrate Noise Generation in Complex Digital Systems:  Efficient Modeling and Simulation Methodology and Experimental Verification”, IEEE JSSC, Vol 37, No. 8, August 2002, p. 1065.
  34. Integrated Circuit Technology for Wireless Communications:  An Overview, Babak Daneshrad, UCLA EE Dept.
  35. “Single-Package Integration of RF Blocks for a 5 GHz WLAN Application”, IEEE Trans Adv Packaging, Vol. 24, No. 3, August 2001, p. 384.
  36. “A Fully-Integrated Single-Chip SOC for Bluetooth”, Frank Eynde, et al., Alcatel, IEEE ISSCC Digest 2001, Paper 13.1, Feb. 2001.
  37. “A 1.5V, 1.5GHz CMOS Low Noise Amplifier”, D. K. Shaeffer and T. H. Lee, IEEE JSSC, Vol. 32, No. 5, May 1997, p. 745.
  38. “Single-Chip 5.8 GHz ETC Transceiver IC with PLL and Demodulation Circuits using SiGe HBT/CMOS”, Toru Masuda, et al., Hitachi, IEEE ISSCC 2002 Technical Digest, paper 5.6, Feb. 2002.
  39. “A 2.4 GHz 0.18 um CMOS Self-Biased Cascode Power Amplifier with 23dBm Output Power”, Sowlati and Leenaerts, Philips Research, IEEE ISSCC 2002 Technical Digest, paper 17.5, Feb. 2002.
  40. “A Highly-Integrated Tri-Band/Quad-Mode SiGe BiCMOS RF-to-Baseband Receiver for Wireless CDMA/WCDMA/AMPS Applications with GPS Capability”, Vladimir Aparin, et al., Qualcomm, San Diego, IEEE ISSCC 2002 Technical Digest, Paper 14.3, Feb. 2002.
  41. “Intra-Chip Wireless Interconnect for Clock Distribution Implemented With Integrated Antennas, Receivers, and Transmitters”, Brian Floyd, Chih-Ming Hung, and Kenneth O., IBM and UFL, IEEE JSSC, vol. 37, No. 5, May 2002, p. 543.
  42. “BICMOS Injection Locking Scheme for Quadrature ….”, IEEE JSSC, July 2002, p. 848.
  43. “ A 7 GHz 1.8 dB NF CMOS LNA”, Toshiba, IEEE JSSC, July 2002, p. 852.
  44. “SiGe BICMOS Transimpedance LNA”, IEEE JSSC, July 2002, p. 889.
  45. “Noise Optimization for LNA’s”, Stanford Univ, IEEE JSSC, August 2002, p. 994.
  46. “1.9 GHz Class AB RF Power Amplifier with Bias Boosting”, Philips Research, ISLPED 2000.
  47. “Fully Integrated Analog Front End for Cable Modem”, IEEE JSSC, July 2002, p. 868.
  48. “A SiGe BICMOS Receiver for Optical Network …”, IEEE JSSC, July 2002, pp. 887-894.
  49. Lecture notes on Bipolar Devices, R. W. Knepper, Stanford University Electrical Engineering Course EE316, 1995.