BOSTON UNIVERSITY COLLEGE OF ENGINEERING

Department of Electrical and Computer Engineering

 

SC571 - VLSI Systems Design: Principles & Applications

Spring Semester 2002

 

Date/Time/Place:  M & W, 10:00AM-12:00 PM, PSY B/45, 64 Cummington Street

 

Instructor:              Prof. Ronald W. Knepper

                        Office Hours:  M/T/W 3:00-6:00 PM, PHO 439

                        e-mail:  rknepper@bu.edu, Phone: 353-0223

                        webpage:  http://people.bu.edu/rknepper/sc571/class.html

 

GTF:              Sulakshana Pasnoor (spasnoor@bu.edu), PHO 313, 353-0036

                        Lab/Office Hours:  M/W 2-5:30 PM, Tu/R 12-2 PM, 4-5:30 PM

 

Course Description: 

Very Large Scale Integrated Circuit design.  Review of MOSFET basics.  Functional module design, combinational logic, programmable logic arrays, finite-state machines, ROM, and RAM.  Fabrication techniques, layout strategies, scalable design rules, design-rule checking, guidelines for testing and testability.  Analysis of factors affecting speed of charge transfer, power requirements, and control and minimization of parasitic effects.  Survey of VLSI applications.  Extensive CAD laboratory accompanies course involving use of MAGIC, CAzM, and the Cadence CAD design package.

 

Prerequisites:  SC311 & SC410

 

Text:  Kang & Leblebici, CMOS Digital Integrated Circuits, McGraw-Hill, 1999 (primary)

      Also, Weste & Eshraghian, Principles of CMOS VLSI Design, Addison Wesley, 1993

References: 1. Baker, Li, & Boyce, CMOS Circuit Design, Layout, and Simulation, IEEE Press, 1998

2. Ken Martin, Digital Integrated Circuit Design, Oxford Univ Press, 2000

3. Douglas J. Smith, HDL Chip Design:  A Practical Guide for Designing, Synthesizing, & Simulating ASICs and FPGAs using VHDL or Verilog, Doone Publications, 1996.

 

Course Methodology: 

The course involves the use of a coordinated set of lectures, labs, and exams to teach VLSI systems design principles and applications.  Labs are designed to expose the student to a set of tools for CMOS design, starting with SPICE circuit simulation and leading to physical layout, design rule checking, and extracted circuit simulation.  Tutorials will be utilized for instructing in the various lab software design tools.

 

Grading:              Three Exams             60%

                        Labs                             35%

                        Homework                   5%

 

                       

 

Schedule of Lectures and Exams:

 

Dates

Topic Description

Text Ref.

1/14

Intro to CMOS Circuits:  N & P device switches, CMOS ckts overview, Moore’s Law

Ch. 1

1/16

AOI Circuits, D register, SRAM Cell, MOS Device Physics, Threshold Voltage

1*, 3.1-3.3

1/23

FET Current Equations, 2nd order effects, Scaling, CAzM & Sigview O/V   (Intro Lab 1)

3.4 - 3.5

1/28

MOS Capacitance, MOSFET Modeling, SPICE Models

3.6, Ch. 4

1/30

Inverter Circuits:  Resistor Load, Static Load, Linear Load, Depletion Load, CMOS

Ch. 5

2/4

Pseudo-NMOS inverter, CMOS Transmission Gate

2.6* - 2.7*

2/6

CMOS Fabrication, Basic CMOS Technology, Interconnect, Physical Design/Layout

Ch. 2

2/11

Cadence Tutorial (in VLSI Lab)                                                             (Handout Lab 2)

 

2/13

Layout Design Rules, CMOS N-Well Design Rules, CMOS Inverter Layout

2.4 - 2.5

2/19

Design Rule Checking, Ckt Model Extraction, Layout vs Schematic, Latchup; Review

3.4* – 3.6*

2/20

Exam I – Chapters 1-5

 

2/25

CMOS Inverter Switching: Rise/Fall & Delay Time Estimation               (Handout Lab 3)

6.1 – 6.3

2/27

Gate Transient Response, Design for Performance, Ring Oscillator, Interconnect Delay

6.4 – 6.6

3/4-3/8

Spring Break (No Class)

 

3/11

Power Dissipation, Charge Sharing, CMOS Combinational Logic Gates

6.7, 7.1-7.2

3/13

CMOS Logic Circuit Transient Response, Complex CMOS AOI Gates, Full Adder

7.3 – 7.4

3/18

Pseudo NMOS Gates, Complementary Pass Transistor Logic               (Handout Lab 4)

7.5

3/20

CMOS Latch Design, Clocked SR & JK Latches

8.1 – 8.3

3/25

CMOS D Latch, Edge-trigger D Flip-Flop

8.4, 8.5

3/27

CMOS Dynamic Logic:  Clocked Logic, Pass Xtr Logic, Domino Logic, Bootstrapping

9.1 – 9.3

4/1

High Performance Dynamic CMOS Logic, NORA, Zipper; Review

9.4 - 9.5

4/3

Exam II – Chapters 6-9

 

4/8

Memory Design, ROM, SRAM

10.1 – 10.3

4/10

Full CMOS SRAM Design, DRAM Design                                              (Handout Lab 5)

10.3 – 10.4

4/17

BiCMOS Logic Circuits

Ch. 12

4/22

Low Power CMOS Design; Chip I/O Circuits, ESD Protection

Ch11, Ch13

4/24

VLSI Design Methodologies

Ch. 14

4/30

Design for Manufacturability

Ch. 15

5/1

Design for Testability; Review

Ch. 16

TBA

Final Exam

 

 

 

 

 

Note:  Text Ref denotes the primary text by Kang & Leblebici, unless indicated with a *, which refers to the alternate text by Weste & Eshraghian.

 

Lateness Penalty:  Homework and Labs will be accepted late (if the solution has not been posted on-line or presented in class) with a penalty of 10% off per day late up to a maximum of 50% off.  Weekends count as one day late.  Homework can not be accepted after the solution has been posted or presented in class.

 

 

 

 

 

 

 

 

Schedule for Labs:

 

 

Lab

Description

Assigned

Due

1

CazM Circuit SimulationInverters and Noise Margin

1/23

2/5

2

Cadence:  Composer, Virtuoso - Physical Layout:  Design of a logic circuit

2/11

2/22

3

Cadence:  Analog Artist - Design for performance – Design a buffer chain

2/25

3/15

4

Cadence:  Composer, Virtuoso, Analog Artist – Design of VCO oscillator

3/18

4/5

5

Cadence:  Design for density & performance – Design of 6 bit adder

4/10

4/30

 

 

 

 

 

 

 

 

 

 

Schedule for Homework:

Assigned

Due

1

Basic CMOS Circuits, Device Threshold and Current Equations

1/16

1/30

2

Inverters, Layout

1/30

2/13

3

Performance, Power, Sizing of Transistors

2/25

3/13

4

CMOS Logic Circuits

3/13

3/27

5

Chip Design Methods, Adder, SRAM, DRAM

4/8

4/22

 

 

LABORATORY RULES

 

Report any problems with system, accounts, or passwords to the system administrator anc@bu.edu.  Report any problems with the assignments, software tools, or grading to the teaching fellow.  Be descriptive and indicate which machine is being used so they can recreate the problem if needed.

 

The design equipment must *NEVER* be turned off.  Terminals and computers should be left on at all times unless otherwise instructed.  Do not "move" mice or keyboards from machine to machine as this completely stops the machines and they must be rebooted.  Please do not attempt to reboot the workstations – call Aaron Caine if problems are encountered.

 

The manuals in the lab are for use in the lab only and are not to be removed.  These manuals are written to be used at a terminal and are not of much practical use outside of the lab.

 

Please try to send output to the printers only when necessary; i.e., only when directed by a lab assignment.  Grad students printing theses and students who like hardcopy of downloads from the net, please take special notice of this request.

 

HOW TO USE THE MAN PAGES:

There are 2 sets installed on the system:  the 'normal' ones, and the ones for the cadtools.  Each manual page program works the same and takes the same arguments.  The only difference is that the program for the cadtools is called cadman, and the normal one is called man.

 

Examples:

If you want help on irsim, type: % cadman irsim

If you want help on arguments to ls, type: % man ls

Read the man pages.

 

 

 

LAB GUIDE LINES

1.  Do the tutorials!  Completing them greatly increases your proficiency with the tools.  Most answers to questions about the tools can be found in the tutorials.

 

2. HOW TO USE THE MAN PAGES:

There are 2 sets installed on the system:  the 'normal' ones, and the ones for the cadtools.  Each manual page program works the same and takes the same arguments.  The only difference is that the program for the cadtools is called cadman, and the normal one is called man.  The man and cadman pages differ somewhat between the MIPS computers and the ALPHAs.  Probably cad and cadman will not work from the HP computers, so rlog to an ALPHA or a MIPS.

Examples:

If you want help on irsim, type: % cadman irsim  and/or man irsim.

If you want help on arguments to ls, type: % man ls

3.  All labs should be in their own directory off your HOME directory (the directory you land in when you first log in: also called ~ for short).  All directory names are the name of the assignment and are specified in the lab write-up.  e.g., for lab1 you make a directory called lab1.

4.  All files must be named as directed in the lab handouts.  These names follow a convention:  all names start with the name of the lab, and end with a name describing the file (exceptions will be noted in the handout).  E.g., in lab1, you make a file called lab1.txt.  Be careful of l ('el') versus 1('one').

5.  All layout files and simulations must use the signal names as directed in the lab handouts.  e.g., if a lab handout explains calling the 3 inputs in0, in1, and in2, label your inputs that way.  Upper and lower case matter: use the case as shown in the handout.

6.  Items 3,4,5 are all necessary to ensure that the labs will be graded and returned quickly.  An automatic grading program helps us find files It will fail if you do not follow to the guidelines.

7.        Some labs have you create a file called lab#.txt after you are done.  In this file you  answer a few questions such as how much time you spent on the lab, ... etc.

8.        For some labs you may be required to hand in hardcopies of the graphs demonstrating your circuit.  Each lab tells you the maximum number of graphs to hand in.  Anybody can print out 35 graphs and hand them all in.  A good engineer can print out a few good ones that explain everything necessary. Be sure your writeup specifies the graphs by number (e.g. Figure 1 or Graph 1), refers to labeled axes, and explains what the curves are or what they mean.

9.  For some labs you will have to measure propagation/settling or rise/fall times of output signals.  Unless told to do otherwise, you should measure the delay from the time your input signal(s) passes 10% of its final value until the output has reached 90% of its final value.

10.  Mail the TF for the class, spasnoor@bu.edu or rknepper@bu.edu, or anc@bu.edu if you have difficulties. System-related difficulties in particular should be sent to anc@bu.edu .

RLOGINS

Lab Remote System Log in: Your full mail address is username@vlsi.bu.edu. There are many hosts available for your remote login to the VLSI lab:  Check out the list posted on the wall.  Many are Simpson’s characters, so that’s easy to remember for many students.

 

There are two ways to log into the vlsi lab cluster, either from:

                                1.  another UNIX system running  X Windows or an Xterminal on campus.

                                2.  a dialup line with a modem (as in from home on a terminal emulator)

Situation 1: in X Windows when logging in from another UNIX workstation running X Windows (acs,bass workstations, etc) or an Xterminal (basement of 111 Cummington St., third floor of Mugar Library, etc.), two procedures must be observed if graphical programs are to be run (VEM, Magic, Workview,matlab, HILO, sigview, DaDSP, SoftPC, etc)

                                - one must give access to the remote system to write graphics to the local X Display

- one must set the remote system to send graphics output to the local X Display

 In other words, if you are on miller in another lab, you must do the following to log into the lab:

                                miller %

                                miller % xhost otto

                                miller % rlogin otto

                                <log into otto>

                                otto % setenv DISPLAY otto:0.0