Boston University                                               Electrical and Computer Engineering

SC571:  VLSI Design Principles      Lab #1 (Inverters:  Tx Sizing and Noise Margin)

 

Name: ______________________________________________________  Due:  2/5/02

 

GOAL:  The purpose of this lab is to explore transistor sizing and its relationship to noise margin.  The lab is also to acquaint you with the CAD tools CAzM and Sigview.  CAzM is a simple SPICE-like simulator, which provides an output in table form.  Sigview is a viewer that will allow you to view the CAzM results graphically.

 

PROBLEM STATEMENT:  Explore several inverter types constructed using the transistor sizes given in the table below.  Use a text editor (Pico is available in the Linux workstations) to define files for the inverter circuit description (cktname.fa) and the command file that applies the stimulus to the circuit (cktname.cmd).  Use CAzM to simulate each circuit.  Then, use Sigview to view and analyze the results of the simulations (dc transfer curves).  Determine the high and low output voltages (VOH and VOL), the (slope = -1) unity gain points (VIL and VIH), and calculate the high and low noise margins for each inverter circuit.  All the pull-down transistors are N-channel enhancement mode with W=2um and L=2um.  The pull-up transistors could be P-channel or N-channel, depending on the circuit, and their sizes are listed in the table below.

 

 

Name

PullUp

Length

PullUp

Width

 

VOL

 

VOH

 

VIL

 

VIH

 

NML

 

NMH

 

CMOS

Inverter

2

4

 

 

 

 

 

 

CMOS

Inverter

2

2

 

 

 

 

 

 

Pseudo-NMOS

Inverter

6

2

 

 

 

 

 

 

Pseudo-NMOS

Inverter

10

2

 

 

 

 

 

 

NENH

Pullup

Inverter

6

2

 

 

 

 

 

 

NENH

Pullup

Inverter

10

2

 

 

 

 

 

 

See Chapter 7, p. 289 in the text (or the class notes) for a definition of Pseudo-NMOS.  The NENH pullup inverter is an NFET saturated load inverter.

SUBMIT:  Put all your files in a subdirectory named lab1 under your login directory.  Hand in the above filled-in table to the GTF (Sulakshana Pasnoor) by the due date.

 

TOOL USAGE:  Refer to the CAzM and Sigview manuals in the box in the VLSI lab for using both tools.  (Please do not take these manuals out of the lab.)  CAzM and Sigview can be accessed from any of the workstations (Dell’s, HP’s, and DEC Alpha’s).  CAzM is running on the Dell machines under Linux.  From the other machines you will need to remotely rlogin to a Dell machine to perform the lab.  Running CAzM on Linux requires that you embed the model file into the .fa file after you specify the circuit schematic.  Place a .eof at the end of the models statement.  The model file (model.txt) is available in the directory home/classes/sc571/.  See the VLSI Lab Administrator, Aaron Caine, if experiencing any problems in running the programs. 

 

Sigview has a function to allow you to directly measure the slope on the screen, which will aid you in locating precisely the (-1) unity gain point.

 

An example of the use of CAzM and Sigview follows on the attached page.

 

                                                                                    R. W. Knepper

                                                                                    January 23, 2002

 

Brief Tutorial:  CAzM and Sigview

 

Example:  CMOS Inverter with Transmission Gate Input

 

CAzM Circuit Schematic Description File:  gateinv.fa

MN1 1 clk in vss cmosn l=1u w=2u

MP1 1 clkbar in vdd cmosp l=1u w=4u

MN2 out 1 vss vss cmosn l=1u w=2u

MP2 out 1 vdd vdd cmosp l=1u w=4u

C1 1 vss 50f

Cout out vss 1p

 

The terms MN1, MP1, etc. give the transistor names first.  Next we list the four transistor terminals in the order “drain, gate, source, substrate” for each transistor in the circuit.  The FET model name cmosn or cmosp must be listed next, followed by the device electrical channel length l and the device width w.  In the above example the channel length is 1 um and the channel width is 2 um.  The units must be specified (u = micro = 10-6, p = pico = 10-12, f = femto = 10-15, etc.).  Blanks may be used as delimiters.

 

The following command file will allow a transient simulation to be performed from 0 to 500ns in 1 ns steps using the SPICE models cmosn and cmosp for the N and P transistors.

 

CAzM Command File:  gateinv.cmd

volt Vdd 5.0

wave in pie {0n 0  100n 0  101n 5  200n 5   201n 0  300n 0  301n 5  400n 5  401n 0  500n 0}

wave clk bit {0011} pw=50n off=0.0 on=5.0 rt=0.1n ft=0.1n

wave clkbar bit {1100} pw=50n off=0.0 on=5.0 rt=0.1n ft=0.1n

plot {in out}

transient 500n 1n

 

The command wave in pie sets a piece-wise linear voltage on terminal ‘in’ with the specified set of pair variables (time, voltage) as given in the statement above.  The wave clk bit command above provides a transient input on node clk with a pulse width of 50 ns, a down-level of 0 volts, an up-level of 5 volts, rise and fall times of 0.1ns, and a logic pattern of 0011.  The command wave clkbar bit generates the complement pulse to the wave clk bit command.  If a dc transient characteristic is desired instead of a transient simulation, the command transfer {in 0 5} must be used in the command file for the input signal rather than a wave command as shown above.

 

CAzM is executed using the command cazm –o nameout gateinv typed in at the prompt.  The –o option generates an output file list called nameout which can be used to plot the output with Sigview.  The term gateinv in the cazm command assumes that both files gateinv.fa and gateinv.cmd exist.  If different names are used for the circuit file and the command file, then both must be included in the command statement.  Remember to embed the model statements for cmosn and cmosp in the .fa file as mentioned before.

 

Sigview is executed by simply typing Sigview outputfilename at the command prompt (where the outputfilename above is nameout).  The program is run by using a series of buttons at the bottom of the screen.  Refer to the Sigview manual for the description of these buttons.