Electrical and Computer Engineering                  BOSTON UNIVERSITY

# SC571:VLSI Design PrinciplesHomework No. 2

This homework assignment covers material primarily from Chapter 2 and Chapter 5 in the Kang and Leblebici textbook plus the class lecture notes.  The assignment is due on Friday, Feb. 15, 2001 by 5:00 PM to Sulakshana Pasnoor (PHO313).

1.  A transmission gate (shown below) is used to charge and discharge a load capacitor connected to Vout.  The N and P switches have +5 and 0 volts on their gates, respectively.  The N device has an electrical W/L = 2/1 and the P device has W/L = 4/1.  Oxide capacitance is assumed to be 3.5 fF/um2 for both devices.  The mobilities are given as 500 cm2/Vsec for the N-FET and 200 cm2/Vsec for the P-FET.  Threshold voltages are determined as follows:

VTN = 0.424 + 0.625 [0.85 + Vsx]1/2 and VTP = -0.576 – 0.474 [0.80 + Vsw]1/2

where Vsx is source-to-substrate voltage and Vsw is source-to-well voltage.

Assume the input has risen to +5 volts and the X-gate is charging the capacitor.  Find the (dc) resistance of the transmission gate for Vout = 0, 1, 2, 3, 4, and 5 volts.  Sketch a plot of Rgate vs Vout.                                                                                                (20 pts)

2.  Determine the appropriate regions of operation and derive the equations for the dc transfer characteristic of the saturated PMOS load inverter shown below.  Write down expressions for the VOH and VOL of the circuit.   Determine the (W/L)load required to obtain a VOL of 0.3 volt or less given the device parameters of question 1 above, VDD = 5 volts, and (W/L)active = 3/1.      (Note:  The quantitative data on the plot below does not apply specifically to this problem!)                                                                       (20 pts)

1. Using linear graph paper and the l CMOS Design Rules given in Chapter 2 in the text, sketch a layout for a simple CMOS transmission gate in a standard N-well CMOS process.  Assume a 1 um technology (l=0.5) with the following masks:

N-well

Active

N Select

P Select

Polysilicon Gate

Contact cut

Metal 1

Assume the NMOS and PMOS devices are to have effective electrical W/L ratios of 5/1 and 10/1, respectively.  You may assume

where DW = 0 and DL = 0.40 um.  Please use color-coded mask levels as suggested in class (Brown=Nwell, Green=Nactive, Yellow=Pactive, Red=Poly, Blue=Metal1, etc.), or identify each mask level clearly with a label.     (20 pts)

1. A Vdd metal M1 wire crosses over the drain regions of two unrelated NMOS transistors that are part of two separate logic circuits built with an N-well CMOS process.  When the power supply Vdd is raised to an over-voltage condition during testing, it is noticed that the two logic circuits fail to give the proper output values, seeming to influence each other’s outputs.
1. Explain what you think is happening in this situation.
2. How could you fix the problem by modifying the CMOS process?
3. How could you fix the problem by modifying the physical layout? (15 pts)

1. Latchup in CMOS technology is a deleterious phenomenon that results in circuit failure and sometime IC destruction (as explained in class) and must obviously be avoided.
1. What is a necessary condition for latchup to occur in a CMOS technology?
2. Explain why guard rings are often used to prevent latchup.         (10 pts)

1. Explain why the following CMOS layout design rules are needed?       (15 pts)
1. Minimum poly width R3
2. Minimum poly spacing R4
3. Minimum gate extension of poly over active R5
4. Minimum contact size R10 or R15
5. Minimum metal width R8
6. Minimum metal space R9
7. Minimum N-well to N active spacing

R. W. Knepper

Feb. 6, 2002