Due: Jan. 30, 2002

1. Design compound CMOS logic gates for the following functions. (Note that X’ = complement of X):

**a. ****Z = (A****·B****·C****·D)’**

**b. ****Z = (A + B + C + D)’**

**c. ****Z = ((A + B)****·(C
+ D))’**

**d. ****Z = (((A****·B)
+ C)****·D)’**

e.
**Z = ((A****·B) + C****·(A +
B))’ ** (10
pts)

2. Show three
different ways of implementing the XOR logic function **Z = A****·(B’) + (A’)****·B**

a. using standard CMOS logic gates (NANDs, NORs, and inverters).

b. using compound CMOS gates with an output inverter.

c. using compound CMOS gates without an output inverter.

List the number of transistors in each case, ignoring input inverters needed to generate A’ & B’. Note that A’ is the complement of A (and similar for B’). (10 pts)

3. Design a set of CMOS gates to implement the sum function

**
S = ABC + (A)(B’)(C’) + (A’)(B)(C’) + (A’)(B’)(C) **

(a) using an implementation comprised only of CMOS NAND gates,

(b) using a compound CMOS logic implementation.

In (b), try to simplify your circuit by eliminating redundant transistors. Assume true and complement inputs are available. Sketch out the circuit schematic at the transistor level. (20 pts)

4.
An
NMOS transistor has a threshold V_{T} of + 0.50 volt when its
source-to-substrate voltage is zero, given that the substrate is uniformly
doped at 2E17 acceptor dopant atoms/cm3 and the gate oxide capacitance is 3.5
fF/um2.

(a)
Determine
an expression for the threshold voltage as a function of source-to-substrate
voltage.

(b)
It
is desired to obtain a threshold voltage of +1.0 volt at 0 volts source
potential (w/r ground). One method
suggested by the engineering team is to provide a separate bias supply for the
substrate, in order to increase the source-to-substrate voltage. What value of Vxx supply would be needed?

(c)
Rather
than use a separate substrate bias generator, another group in Engineering is
suggesting to use a threshold adjustment implant in the fabrication. Assuming the implant acts as a sheet charge
at the oxide-silicon interface (via the term Q_{fc}), what dose is
needed to obtain V_{TN} = 1 volt at V_{sx} = 0? Would you use acceptor (N_{A}) or
donor (N_{D}) atoms? (20 pts)

5. Calculate noise
margins for a CMOS inverter operating at V_{DD} = 3.3 volt with V_{TN}
= 0.75 volt, V_{TP} = -0.75 volt, and b_{N}
= b_{P}. If b_{N} = 2 b_{P}, what are the new noise margins? (20 pts)

6. Design a
five-stage ring oscillator built with pseudo-NMOS inverters and write out the
SPICE code to represent the circuit (for numerical simulation). Assume each stage is loaded with a 50 fF
equivalent wire capacitance. Assume all
N and P devices have L_{eff} = 0.25 um, the N-FET’s have W/L =
8/1. Design the P-FET W/L to achieve a
down level of 0.2 volt, given a full up level input condition. Roughly estimate the device source and drain
dimensions for the SPICE coding.
Transistor model names are assumed to be **NMOS** and **PMOS**. Use the simple MOSFET equations given in the
text and in class for the device currents, assuming m_{N} = 2.5 x m_{P},
V_{TN} = +0.75 volt, V_{TP} = -0.75 volt, and V_{DD} =
3.3 volt. You may assume C_{ox}
= 3.5 fF/um^{2}. (20 pts)

R. W. Knepper

Jan. 16, 2002