Boston University                                 Electrical and Computer Engineering

SC500:  RF/Analog IC Design                            Lab #1:  BICMOS Device Characteristics

      Due:  9/24/02


GOAL:   The goal of this lab assignment is to layout simple CMOS and NPN bipolar transistors and to simulate their dc and small-signal ac device characteristics, with models extracted from the layouts, using the basic Cadence CAD tools.


DESIGN:    Using Cadence Virtuoso, design and layout simple CMOS and NPN transistors in 0.25 um technology and extract device models from the layouts.  You are going to use tsmc025 (0.30 um) NFET and PFET (four terminal) transistors found in the model library and a generic 0.25 um NPN bipolar transistor obtained from the NCSU analog library.  Dimensions should be W=5 um and L=0.30 um (design values) for the CMOS devices and a single emitter stripe = 0.30 um x 5 um for the NPN transistor.  Be sure that substrate (and N-well) contacts are included in your layouts.  The NPN should have single base and collector contacts, in addition to the single emitter stripe.  Use DRC to check for design rule errors and LVS to guarantee logic-versus-schematic consistency before doing your model extraction.


SIMULATION:  Use Cadence Composer (schematic capture tool) to build simple biasing circuits around your NPN and CMOS transistors for the purpose of running the dc and small signal ac simulations.  Once the schematic is complete with dc voltage source(s), small-signal ac input(s), and any resistor or capacitor elements you may want to include, use Analog Environment to simulate the circuit.  It is advisable to first simulate based on the schematic models alone before doing the simulations with your extracted models.  (You will probably not see any major differences when comparing results.)


RESULTS:  Generate and plot the following simulated results.

  1. DC drain-source characteristics for the NFET and PFET transistors (IDS versus VDS with VGS as the parameter).  Use VDD = 2.5 volts (= max VDS and max VGS).  Determine ION per um of gate width for both CMOS transistors.
  2. DC collector characteristics for the NPN transistor (IC versus VCE with IB as the parameter).  Again, the collector supply voltage VCC will be the same as VDD = 2.5 volts.  Start with IB = 0 and increment until you obtain a max IC of 1 mA.  Determine the base width modulation factor l from the slope of the characteristic in the so-called active region.
  3. DC gate characteristics for the NFET and PFET transistors (log IDS versus VGS with VDS = 0.25V and 2.5V).  Estimate the threshold voltages and transconductance values from these plots.
  4. Gummel plot for the NPN transistor (log IC and log IB versus VBE at VCE = 2.5V).  Determine and plot the dc b versus log IC from the Gummel plot. 
  5. Determine the NFET and PFET fT values from the plot of small-signal ac IDS/IG versus log frequency, and extrapolate to the unity gain point.  Since IG can be related to VGS through the gate capacitance Cg, one can show that fT = gm/2pCg from MOSFET theory.
  6. Determine the fT value for the NPN transistor from a plot of small-signal ac b = IC/IB versus log frequency, and again extrapolate to the unity gain point.  


METHODOLOGY:  The DC results for parts 1-4 above can be obtained by applying a fixed dc bias to the drain (or collector) and sweeping a dc voltage or current on the input gate (or base) terminal.  The dc bias on the input gate (or base) will automatically be set by sweeping this voltage (or current) through appropriate values.  In parts 5 and 6, you will need to apply dc bias to the drain (or collector) and the gate (or base), as well as to apply a small-signal sine wave source to the input for obtaining the small-signal ac output currents.  Sometimes this may cause numerical convergence problems with the matrix solution, which can often be solved by putting a resistor in series with the ac source (and/or dc bias), putting these combinations in parallel, and then plotting the input ac current directly into the gate (or base).  A bit of trial and error will usually fix the convergence problem and allow an accurate solution.


WRITEUP:  Your output will be a hard copy report comprised of printed copies of your individual basic circuit schematics, symbols, simulation waveforms, layouts, and requested output data.  Hand in the report to Prof. Knepper when complete.


TUTORIALS: (How to learn Cadence Composer, DRC, Virtuoso, LVS, Extract, and Analog Environment?)  If you have never used the Cadence tools listed above, you will want to go through the Cadence tutorial found on the NCSU web site, or available from Prof. Knepper.  First, try building a simple inverter using the tutorial, and then go through the basic simulation exercises given therein.


                                                                                                            R. W. Knepper, 9/9/02