Publications & Patents: 

Ronald W. Knepper

 
Publications and External Presentations:
  • The CMOS-Driven Semiconductor Industry Technology Roadmap and Future Projections, invited seminars at Carnegie Mellon University, Pittsburgh, PA, RW Knepper;  Feb. 1998, Feb. 1999.
  • IBM TCAD Tool Set for Device Design & Optimization, invited seminars at Stanford University and UC Berkeley, RW Knepper; Nov. 1994, Dec. 1994, Feb. 1995.
  • Technology CAD at IBM, invited presentation, Workshop on Technology CAD Systems, 1993 SISDEP Symposium, Vienna, RW Knepper, et al., Springer-Verlag, pp. 25-62;  Sept. 1993.
  • Modeling the Small-Emitter Effect in Polysilicon-Emitter Transistors, IEEE 1992 BCTM,  LF Wagner, et al., pp. 130-133;  Oct. 1992.
  • A Comparative Device and Performance Analysis Between a SiGe Epitaxial-Base HBT and a Si Double-Poly I/I BJT NPN Structure, IEEE 1992 BCTM, MM Pelella, et al., pp. 46-49; Oct. 1992.
  • Device and Circuit Modeling for Advanced Bipolar and BICMOS at IBM, invited presentation, SRC Topical Research Conference on TCAD, Univ of Ill, RW Knepper;  Oct. 1991.
  • Modeling Advanced Bipolar Devices for High Performance Applications, invited paper, IEEE IEDM Technical Digest, San Francisco, RW Knepper, pp. 177-180;  Dec. 1990.
  • A 40 GHz Strained-Layer SiGe Heterojunction Bipolar Transistor Fabricated With Low Temperature Epi, IEEE IEDM Technical Digest, late news paper, S. Fischer, RW Knepper, et al., pp. 890-892;  Dec. 1989.
  • Problems in High Performance Bipolar Device Modeling, invited paper, IEEE Bipolar Circuits and Technology Meeting, Proc. 1987 BCTM, Minneapolis, RW Knepper, pp. 1-4;  Sept. 1987.
  • Advanced Bipolar Transistor Modeling:  Process and Device Simulation Tools for Today's Technology,  IBM J Research & Development, Vol. 29, No. 3, Knepper, Gaur, Chang, & Srinivasan, pp. 218-228;  May 1985.
  • Two-dimensional Process Modeling:  A Description of the SAFEPRO Program, IBM J Research & Development, Vol. 29, No. 3, RR O'Brien, et al., pp. 229-241;  May 1985.
  • Chip Substrate Resistance Modeling Technique for Integrated Circuit Design, IEEE Int'l Symposium on Circuits and Systems, vol. 2, pp. 762-765, May 1983; and IEEE Trans Computer-Aided Design, Vol. CAD-3, No. 2, pp. 126-134, April 1984;  Johnson, Knepper, Marcello, and Wang.
  • Dynamic Depletion Mode:  An E/D MOSFET Circuit Method, IEEE ISSCC Digest of Technical Papers, pp. 16-17, RW Knepper;  Feb. 1978.
  • Dynamic Depletion Mode:  An E/D MOSFET Circuit Method for Improved Performance, IEEE Journal of Solid-State Circuits, Vol.SC-13, No. 5, RW Knepper, pp. 542-548;  Oct. 1978.
  • Electrical Fluctuations in Silicon Double Injection Devices, Solid-State Electronics, Vol. 15, No. 1, RW Knepper and AG Jordan, pp. 59-67;  Jan. 1972.
  • Double Injection in P/pi/N Silicon Devices, Solid-State Electronics, Vol. 15, No. 1, RW Knepper and AG Jordan, pp. 45-48;  Jan. 1972.
  • Fluctuations in the Pre-Breakdown Region of Double Injection PIN Diodes, Appl Phys Letters, vol. 6, No. 7, AG Jordan and RW Knepper, pp. 126-128, April 1965.
Patents:
  • High Speed DRAM Local Bit Line Sense Amplifier, Patent #        ; Issued August 2002;  RH Dennard and RW Knepper.
  • Vertical-Gate CMOS Compatible Lateral Bipolar Transistor, Patent #5446312;  Issued 8/29/95;  CM Hsieh, LC Hsu, S-N Mei, RW Knepper, and LF Wagner Jr.
  • Novel Vertical-Gate CMOS Compatible Lateral Bipolar Transistor, Patent #5371022;  Issued 12/6/94;  CM Hsieh, LC Hsu, S-N Mei, RW Knepper, and LF Wagner Jr.
  • A Novel Vertical-Gate CMOS-Compatible Lateral Bipolar Transistor, Patent #5341023;  Issued 8/23/94;  CM Hsieh, LC Hsu, RW Knepper, S-N Mei, and LF Wagner, Jr.
  • Method for Controlling Interfacial Oxide at a Polycrystalline/Monocrystalline Silicon Interface, Patent #5194397; Issued 3/16/93;  R Cook, R Knepper, S Kulkarni, R Lange, P Ronsheim, S Subbanna, M Tejwani, and B Yun.
  • Memory Cell with Active Device for Saturation Capacitance Discharge Prior to Writing, Patent #4922455;  Issued 5/1/90;  R Wong, W chin R Knepper, R Dussault, and F Wernicke.
  • Read-Only Memory Including An Isolation Network Connected Between the Array of Memory Cells and the Output Sense Amplifier Whereby Reading Speed Is Enhanced, Patent #4651302;  Issued 3/17/87;  RD Kimmel, RW Knepper, and R Levi.
  • Word Group Redundancy Scheme, Patent #4462091;  Issued 7/24/84;  RW Knepper, P Ludlow, and J Petrosky.
  • Memory Cell With Switchable Upper and Lower Word Lines, Patent #4460984;  Issued 7/17/84;  RW Knepper.
  • Field Effect Transistor (FET) Circuit Utilizing Substrate Potential for Turning Off Depletion Mode Devices, Patent #4093875;  Issued 6/6/78;  R W Knepper.
  • Enhancement/Depletion Mode Field Effect Transistor Driver, Patent #4071783;  Issued 1/31/78;  RW Knepper.
  • Narrow Channel Length MOS Field Effect Transistor with Field Protection Region for Reduced Source-Substrate Capacitance, Patent #4350991;  Issued 9/21/82;  WS Johnson and RW Knepper.
  • Method for Forming A Narrow Channel Length MOS Field Effect Transistor, Patent #4078947;  Issued 3/14/78;  WS Johnson and RW Knepper.
  • Semiconductor Device Having Electrically Insulating Barriers for Surface Leakage Sensitive Devices and Method of Forming, Patent #3961355;  Issued 6/1/76;  S Abbas, CS Chang, SB Freeman, and RW Knepper.
  • Common BUS Driver Complementary Protect Circuit, Patent #3938008;  Issued 2/10/76;  RW Knepper, R Lane, P Ludlow, and B Moore.
     
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Comments  |  24 November 1998