Masters Research Thesis

I moved from Colorado State University to University of California, Riverside to continue my research with Dr. Walid Najjar. As part of my MS Thesis, I worked on the Cameron Project between Fall 2000 - Summer 2001. I successfully defended my research contribution on Oct 5th 2001. Check below for more resources on my thesis titled -  'Compile-time Area Estimation for LUT-based FPGAs'.

• Slides for the defense presentation (in PowerPoint)

• Thesis Report [ps ] [doc]

• Poster (3rd prize at the 3rd Annual Industry Day, Dec 5th 2001, UC Riverside)

• Paper (published in the proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines [FCCM 2002] )

Abstract

The Cameron Project has developed a system for compiling codes written in a high-level language called SA-C, to FPGA-based reconfigurable computing systems. In order to exploit the parallelism available on the FPGAs, the SA-C compiler performs a large number of optimizations such as full loop unrolling, loop fusion and strip-mining. However, the area on the FPGA is limited and therefore the compiler needs to know the effect of compiler optimizations on the FPGA area. In this thesis we present a compile-time area estimation technique to guide the SA-C compiler optimizations. We demonstrate our technique for a variety of benchmarks written in SA-C. Experimental results show that our technique achieves an error rate of 2.5 % for small image-processing operators and 5.0 % for larger benchmarks, as compared to the synthesis/mapping. The estimation time is in the order of 1 millisecond as compared to order of minutes for a synthesis tool.