COMMENT * 7.4us per pixel, 5.32us integration time - set to supress ghosting ---DPC 8/22/2004 VDETCOM set to -2.8V (-1.0 V of reverse bias) - DPC 8/21/2004 further reduced integration time to 1.2us (3.4us total) - DPC 8/21/04 Waveform tables for Aladdin II IR array to be used with ARC-46 = 8x IR video processor and Gen II = ARC22 = 250 MHz timing board. Started April 2, 2003 and derived from Gen II V1.7 Aladdin code. * ; Temporary definitions for V1.7 compatability AD EQU $000001 ; Bit to start A/D conversion XFER EQU $000002 ; Bit to transfer A/D counts into the A/D FIFO ;CLK_ZERO EQU 0 ; Zero volts out on clock driver line SXMIT EQU $00F0E0 ; Transmit 8 pixels from two coadder boards F_DLY EQU $100000 ; ; Definitions of readout variables CLK2 EQU $002000 ; Clock driver board lower half CLK3 EQU $003000 ; Clock driver board upper half VIDEO EQU $000000 ; Video processor board switches ; Various delay parameters VP_DLY EQU $1C0000 ; Video delay time for 2.0 microsec/pixel VP_DLY_PT EQU $B80000 ; Pass through video delay time for 10.0 microsec/pixel DLY0 EQU $280000 ; Pixel readout delay parameter DLY1 EQU $060000 ; Frame sync delay parameter at 240ns DLY2 EQU $980000 DLY5 EQU $280000 ; Pixel readout delay parameters DLY6 EQU $0C0000 DLY7 EQU $200000 DLY8 EQU $0C0000 DLY200 EQU $050000 ; Delay of 200ns DLGR EQU $CC0000 ; Delay for Global Reset (was $AC 8/20/04) DTRS EQU $060000 ; Trs Overlap of Slow Clocks 240ns D10U EQU $900000 ; Tre = Tro Slow Clock for Row Selection Stability DTW EQU $080000 ; Tw Fast Sync Time (200ns + 40ns exec = 240ns) DTA EQU $500000 ; Ta Delay before pixel clocks ; Values for IR clock driver board. The clock driver board needs to ; jumpered for negative voltages only, and R70 = 10k ohms needs to be ; changed to 6.62 kohm to reach -7.5 volts. ;MAX_V EQU 7.5 ; Maximum voltage from clock driver board ;MAX_V2 EQU 15.0 ; 2 x MAX_V ;CLK_HI EQU 6.0 ; High Clock voltage ;CLK_LO EQU 1.0 ; Low Clock voltage ; Values for displaying clocks on Logic Analyzer with CCD clock driver board MAX_V EQU 7.5 ; Abs Maximum voltage from the clock driver board MAX_V2 EQU 15.0 ; 2 x MAX_V ;CLK_HI EQU 4.0 ; High Clock voltage ;CLK_LO EQU 0.0 ; Low Clock voltage HI_CLK EQU 0.0 LO_CLK EQU -6.0 CLK_HI EQU ((MAX_V+HI_CLK)/MAX_V)*4095 ; CLK_LO EQU ((MAX_V+LO_CLK)/MAX_V)*4095 ; CLK_ZERO EQU 4095 ; ; Values for a default IR clock driver board that runs from 0 to -5 volts. ;MAX_V EQU 5.0 ; Maximum voltage from clock driver board ;MAX_V2 EQU 10.0 ; 2 x MAX_V ;CLK_HI EQU 4.0 ; High Clock voltage ;CLK_LO EQU 1.0 ; Low Clock voltage S_DLY EQU $100000 ; SLOW clock delay ; Define switch state bits for CLK2 = bottom of clock board VROWON EQU 4 ; Bias to row enable CLock 2 VDDCL_T EQU 8 ; VDD Clamp Clock 3 RDES EQU $10 ; Row deselect Clock 4 VRSTOFF EQU $20 ; Global reset = VrstG Clock 5 VRSTR EQU $40 ; Row reset bias Clock 6 VGGCL_T EQU $80 ; Column Clamp Clock Clock 7 SSYNC EQU $100 ; Slow Sync Clock 8 S1 EQU $200 ; Slow phase 1 Clock 9 S2 EQU $400 ; Slow phase 1 Clock 10 SOE EQU $800 ; Odd/Even row select Clock 11 ; Define switch state bits for CLK3 = top of clock board FSYNC EQU 1 ; Fast sync Clock 12 F1 EQU 2 ; Fast phase 1 Clock 13 F2 EQU 4 ; Fast phase 2 Clock 14 VNROW_T EQU $100 ; Slow Shift Reg Bias Clock 19 VNCOL_T EQU $200 ; Fast Shift Reg Bias Clock 20 ; Aladdin II DC bias voltage definition VGGCL EQU 0.0 ; Column Clamp Clock, warm VDDCL EQU -3.8 ; Column Clamp Bias VDDUC EQU -4.0 ; Negative Unit Cell Bias VNROW EQU -6.0 ; Negative row supply VNCOL EQU -6.0 ; Negative column supply VROWOFF EQU 0.0 ; Bias for Row enable transistors VDDOUT EQU -1.5 ; Drain voltage for drivers VDETCOM EQU -2.95 ; Detector Common (-1.0 V reverse bias) IREF EQU -2.5 ; Reference current for Iidle and Islew VSSOUT EQU 1.0 ; Source follower load voltage VSSCOM EQU 0.0 ; Source follower common VP_T EQU 0.0 ; Return for shift regisiter logic supply VTEND EQU 0.0 ; Bias for diagnostic output BIAS_VAL EQU 1.0 ; Bias Value for Zero VDDCL_CLK EQU ((MAX_V+VDDCL)/MAX_V)*4095 ; VGGCL_CLK EQU ((MAX_V+VGGCL)/MAX_V)*4095 ; VNROW_CLK EQU ((MAX_V+VNROW)/MAX_V)*4095 ; VNCOL_CLK EQU ((MAX_V+VNCOL)/MAX_V)*4095 ; VRSTHI_CLK EQU ((MAX_V-3.5)/MAX_V)*4095 ; VRSTLO_CLK EQU ((MAX_V-5.5)/MAX_V)*4095 ; ; BIAS_SOURCE EQU ((MAX_V+BIAS_VAL)/MAX_V)*4095 ;BIAS_SOURCE EQU 2180 BIAS_SOURCE EQU 2400 BIAS_ZERO EQU 2048 BIAS_SOURCE EQU (VSSOUT+5.0)/10.0*4095) ; A/D converter voltage reference ADREF EQU 2.71 ; Between 0 and 2.5 volts. 2.5 = min. gain **NOTE** Reference ; Voltage needed to be bumped up on the DAC to get the 2.5 at the ADC ; Video offset variable OFFSET EQU $940 SPOFFSET EQU $700 ; The following are the ADC offsets for each quadrant ; Change these to balance the no-light data numbers for ; each quadrant ; ; 6/9/2004 DPC all had been set to $7BE, balancing now ; OFFSETA EQU $7BE ; LL target=55k ;OFFSETC EQU $940 ; Test value OFFSETB EQU $7BE ; LR " OFFSETC EQU $7BE ; UL target=55k OFFSETD EQU $7BE ; UR " ;SXMIT EQU $00F1C0 ; Transmit A/Ds = 0 to 7 ;SXMIT EQU $00F0C0 ; Transmit A/Ds = 0 to 3 ;SXMIT EQU $00F040 ; Transmit A/Ds = 0 to 1 ;SXMIT EQU $00F0C2 ; Transmit A/Ds = 2 to 3 ;SXMIT EQU $00F000 ; Transmit A/D = 0 ;SXMIT EQU $00F041 ; Transmit A/D = 1 ;SXMIT EQU $00F082 ; Transmit A/D = 2 ;SXMIT EQU $00F0C3 ; Transmit A/D = 3 ;SXMIT DC $00F3C0 ; x16 Transmit A/D 0 to 15 ;SXMIT DC $00F7C0 ; x32 Transmit A/D 0 to 31 ; Copy of the clocking bit definition for easy reference ; DC CLK2+DELAY+SSYNC+S1+S2+SOE+RDES+VRSTOFF+VRSTR+VROWON ; DC CLK3+DELAY+FSYNC+F1+F2 FRAME_INIT DC END_FRAME_INIT-FRAME_INIT-1 DC CLK2+DLY1+SSYNC+S1+S2+SOE+RDES+VRSTOFF+VRSTR+000000 DC CLK2+DLY1+00000+S1+S2+SOE+RDES+VRSTOFF+VRSTR+000000 DC CLK2+DLY1+SSYNC+S1+S2+SOE+RDES+VRSTOFF+VRSTR+000000 DC CLK2+DLY1+SSYNC+00+S2+SOE+RDES+VRSTOFF+VRSTR+000000 DC CLK2+DLY1+SSYNC+S1+S2+SOE+RDES+VRSTOFF+VRSTR+000000 END_FRAME_INIT FRAME_INIT_RESET DC END_FRAME_INIT_RESET-FRAME_INIT_RESET-1 DC CLK2+DLGR+SSYNC+S1+S2+SOE+RDES+0000000+VRSTR+000000 DC CLK2+DTRS+SSYNC+S1+S2+SOE+RDES+VRSTOFF+VRSTR+000000 END_FRAME_INIT_RESET CLOCK_ROW_1 DC END_CLOCK_ROW_1-CLOCK_ROW_1-1 DC CLK2+DLY1+SSYNC+S1+S2+SOE+RDES+VRSTOFF+VRSTR+000000 DC CLK2+DLY1+SSYNC+S1+00+SOE+RDES+VRSTOFF+VRSTR+000000 DC CLK3+DTW+00000+F1+F2 DC CLK3+DTW+FSYNC+F1+F2 DC CLK3+DTW+FSYNC+00+F2 DC CLK3+DTA+FSYNC+F1+F2 END_CLOCK_ROW_1 CLOCK_ROW_2 DC END_CLOCK_ROW_2-CLOCK_ROW_2-1 DC CLK2+DLY1+SSYNC+S1+00+SOE+RDES+VRSTOFF+VRSTR+000000 DC CLK2+DLY1+SSYNC+S1+00+000+RDES+VRSTOFF+VRSTR+000000 DC CLK3+DTW+00000+F1+F2 DC CLK3+DTW+FSYNC+F1+F2 DC CLK3+DTW+FSYNC+00+F2 DC CLK3+DTA+FSYNC+F1+F2 END_CLOCK_ROW_2 CLOCK_ROW_3 DC END_CLOCK_ROW_3-CLOCK_ROW_3-1 DC CLK2+DLY1+SSYNC+S1+S2+SOE+RDES+VRSTOFF+VRSTR+000000 DC CLK2+DLY1+SSYNC+00+S2+SOE+RDES+VRSTOFF+VRSTR+000000 DC CLK3+DTW+00000+F1+F2 DC CLK3+DTW+FSYNC+F1+F2 DC CLK3+DTW+FSYNC+00+F2 DC CLK3+DTA+FSYNC+F1+F2 END_CLOCK_ROW_3 CLOCK_ROW_4 DC END_CLOCK_ROW_4-CLOCK_ROW_4-1 DC CLK2+DLY1+SSYNC+00+S2+SOE+RDES+VRSTOFF+VRSTR+000000 DC CLK2+DLY1+SSYNC+00+S2+000+RDES+VRSTOFF+VRSTR+000000 DC CLK3+DTW+00000+F1+F2 DC CLK3+DTW+FSYNC+F1+F2 DC CLK3+DTW+FSYNC+00+F2 DC CLK3+DTA+FSYNC+F1+F2 END_CLOCK_ROW_4 RESET_ROW_1 DC END_RESET_ROW_1-RESET_ROW_1-1 DC CLK2+DTRS+SSYNC+S1+S2+SOE+RDES+VRSTOFF+VRSTR+VROWON DC CLK2+D10U+SSYNC+S1+00+SOE+RDES+VRSTOFF+00000+VROWON END_RESET_ROW_1 RESET_ROW_2 DC END_RESET_ROW_2-RESET_ROW_2-1 DC CLK2+D10U+SSYNC+S1+00+000+RDES+VRSTOFF+00000+VROWON END_RESET_ROW_2 RESET_ROW_3 DC END_RESET_ROW_3-RESET_ROW_3-1 DC CLK2+DTRS+SSYNC+S1+S2+SOE+RDES+VRSTOFF+VRSTR+VROWON DC CLK2+D10U+SSYNC+00+S2+SOE+RDES+VRSTOFF+00000+VROWON END_RESET_ROW_3 RESET_ROW_4 DC END_RESET_ROW_4-RESET_ROW_4-1 DC CLK2+D10U+SSYNC+00+S2+000+RDES+VRSTOFF+00000+VROWON DC CLK2+DTRS+SSYNC+S1+S2+SOE+RDES+VRSTOFF+VRSTR+000000 END_RESET_ROW_4 ; Video processor bit definitions ; Bit #3 = Move A/D data to FIFO (high going edge) ; Bit #2 = A/D Convert (low going edge to start conversion) ; Bit #1 = Reset Integrator (=0 to reset) ; Bit #0 = Integrate (=0 to integrate) PAD_TIM EQU $180000 ; Pixel PAD Time INT_TIM EQU $130000 ; Pixel Sample Time ADC_TIM EQU $180000 ; ADC Hold/Conversion Time SXM_TIM EQU $980000 ; Pixel Transmit Delay ADC_CNV EQU $0A0000 ; ADC Sample Time RD_COL_PIPELINE ;; This code intiates the pipeline of pixels for each row DC END_RD_COL_PIPELINE-RD_COL_PIPELINE-1 DC CLK3+000+FSYNC+F1+00 ; Select Pixel 1 (40ns) DC VIDEO+PAD_TIM+%0111 ; Pad Delay - 40ns DC VIDEO+ADC_TIM+%0111 ; Hold No Pixel (1us) DC VIDEO+$000000+%0101 ; Move No Pixel (40ns) DC VIDEO+$000000+%0101 ; Place for SXMIT (40ns) DC VIDEO+SXM_TIM+%0101 ; Settling time (480ns) DC VIDEO+INT_TIM+%0110 ; Integrate Pixel 2 (760ns) DC VIDEO+$000000+%0111 ; Stop Integration DC VIDEO+ADC_CNV+%0011 ; Start A/D convert Pixel 2 (400ns) DC CLK3+DTW+FSYNC+F1+F2 ; Deselect Pixel 1 (240ns) DC CLK3+000+FSYNC+00+F2 ; Select Pixel 3 (40ns) DC VIDEO+PAD_TIM+%0111 ; Pad Delay - 40ns DC VIDEO+ADC_TIM+%0111 ; Hold A/D convert sig Pixel 2 (1us) DC VIDEO+$000000+%1101 ; Move A/D data to FIFO Pixel 2 (40ns) DC $00F7C0 ; SXMIT the Previous Pixel 2 - X32 (40ns) DC VIDEO+SXM_TIM+%0101 ; Settling time (480ns) DC VIDEO+INT_TIM+%0110 ; Integrate Pixel 3 (760ns) DC VIDEO+$000000+%0111 ; Stop Integration DC VIDEO+ADC_CNV+%0011 ; Start A/D convert Pixel 3 (400ns) DC CLK3+DTW+FSYNC+F1+F2 ; Deselect Pixel 3 (240ns) END_RD_COL_PIPELINE ; Video processor bit definitions ; Bit #3 = Move A/D data to FIFO (high going edge) ; Bit #2 = A/D Convert (low going edge to start conversion) ; Bit #1 = Reset Integrator (=0 to reset) ; Bit #0 = Integrate (=0 to integrate) ; DC CLK2+$000000+FSYNC+F1+F2+RST RD_COLS DC END_RD_COLS-RD_COLS-1 ; DC CLK3+000+FSYNC+F1+00 ; Select Pixel 2 (40ns) DC VIDEO+PAD_TIM+%0111 ; Pad Delay - 40ns DC VIDEO+ADC_TIM+%0111 ; Hold A/D convert sig Pixel 1 (1us) DC VIDEO+$000000+%1101 ; Move A/D data to FIFO Pixel 1 (40ns) DC $00F7C0 ; SXMIT the Previous Pixel 1 - X32 (40ns) DC VIDEO+SXM_TIM+%0101 ; Settling time (480ns) DC VIDEO+INT_TIM+%0110 ; Integrate Pixel 2 (760ns) DC VIDEO+$000000+%0111 ; Stop Integration DC VIDEO+ADC_CNV+%0011 ; Start A/D convert Pixel 2 (400ns) DC CLK3+DTW+FSYNC+F1+F2 ; Deselect Pixel 1 (240ns) DC CLK3+000+FSYNC+00+F2 ; Select Pixel 3 (40ns) DC VIDEO+PAD_TIM+%0111 ; Pad Delay - 40ns DC VIDEO+ADC_TIM+%0111 ; Hold A/D convert sig Pixel 2 (1us) DC VIDEO+$000000+%1101 ; Move A/D data to FIFO Pixel 2 (40ns) DC $00F7C0 ; SXMIT the Previous Pixel 2 - X32 (40ns) DC VIDEO+SXM_TIM+%0101 ; Settling time (480ns) DC VIDEO+INT_TIM+%0110 ; Integrate Pixel 3 (760ns) DC VIDEO+$000000+%0111 ; Stop Integration DC VIDEO+ADC_CNV+%0011 ; Start A/D convert Pixel 3 (400ns) DC CLK3+DTW+FSYNC+F1+F2 ; Deselect Pixel 3 (240ns) END_RD_COLS ; Video processor bit definition ; Bit #3 = Move A/D data to FIFO (high going edge) ; Bit #2 = A/D Convert (low going edge to start conversion) ; Bit #1 = Reset Integrator (=0 to reset) ; Bit #0 = Integrate (=0 to integrate) LAST_8INROW DC END_LAST_8INROW-LAST_8INROW DC CLK3+000+FSYNC+F1+00 ; Select Pixel 2 (40ns) DC VIDEO+PAD_TIM+%0111 ; Pad Delay - 40ns DC VIDEO+ADC_TIM+%0111 ; Hold A/D convert sig Pixel 1 (1us) DC VIDEO+$000000+%1101 ; Move A/D data to FIFO Pixel 1 (40ns) DC $00F7C0 ; SXMIT the Previous Pixel 1 - X32 (40ns) DC VIDEO+SXM_TIM+%0101 ; Settling time (480ns) DC VIDEO+INT_TIM+%0110 ; Integrate Pixel 2 (760ns) DC VIDEO+$000000+%0111 ; Stop Integration DC VIDEO+$0A0000+%0011 ; Start A/D convert Pixel 2 (40+40ns) DC CLK3+DTW+FSYNC+F1+F2 ; Deselect Pixel 1 (240ns) END_LAST_8INROW RD_COL_NOXFER DC END_RD_COL_NOXFER-RD_COL_NOXFER-1 DC END_RD_COLS-RD_COLS-1 DC VIDEO+$040000+%0111 ; Settling time DC CLK3+DTW+FSYNC+F1+00 ; Select Pixel 2 (40ns) DC VIDEO+$000000+%0111 ; Settling time DC VIDEO+$280000+%0111 ; Integrate (5120ns) DC VIDEO+$0A0000+%0111 ; Settling Time = 400ns DC VIDEO+$010000+%0111 ; Start A/D convert (40+40ns) DC VIDEO+$900000+%0111 ; Hold A/D convert sig (400ns) DC VIDEO+$000000+%0111 ; Move A/D data to FIFO DC VIDEO+$000000+%0111 ; Move A/D data to FIFO DC CLK3+DTW+FSYNC+F1+F2 ; Deselect Pixel 2 (40ns) DC VIDEO+$000000+%0111 ; Move A/D data to FIFO DC VIDEO+$120000+%0111 ; Settling time DC VIDEO+$040000+%0111 ; Settling time DC CLK3+DTW+FSYNC+00+F2 ; Select Pixel 2 (40ns) DC VIDEO+$000000+%0111 ; Settling time DC VIDEO+$280000+%0111 ; Integrate (5120ns) DC VIDEO+$0A0000+%0111 ; Settling Time = 400ns DC VIDEO+$010000+%0111 ; Start A/D convert (40+40ns) DC VIDEO+$900000+%0111 ; Hold A/D convert sig (400ns) DC VIDEO+$000000+%0111 ; Move A/D data to FIFO DC VIDEO+$000000+%0111 ; Move A/D data to FIFO DC CLK3+DTW+FSYNC+F1+F2 ; Deselect Pixel 1 (40ns) DC VIDEO+$000000+%0111 ; Move A/D data to FIFO DC VIDEO+$120000+%0111 ; Settling time + Integrator Reset(600+40ns) END_RD_COL_NOXFER ;RD_COLS_NOXFER ; DC END_RD_COLS_NOXFER-RD_COLS_NOXFER-1 ; DC CLK3+0000+FSYNC+00+F2 ; DC VIDEO+$040000+%0101 ; Reset integrator ; DC VIDEO+$000000+%0111 ; Settle Time ; DC VIDEO+$0A0000+%0110 ; Integrate ; DC VIDEO+$010000+%0111 ; Settling time = 400 nsec ; DC VIDEO+$010000+%0011 ; Start A/D convert ; DC VIDEO+$180000+%0111 ; Hold A/D input at least 400 ns ; DC VIDEO+$180000+%0111 ; Hold A/D input at least 400 ; DC VIDEO+$000000+%1111 ; Move A/D data to FIFO ; DC CLK3+0000+FSYNC+F1+F2 ; DC VIDEO+$0F0000+%0111 ; Settling time ; DC VIDEO+$0F0000+%0111 ; Settling time ; DC CLK3+0000+FSYNC+F1+00 ; DC VIDEO+$040000+%0101 ; Reset integrator ; DC VIDEO+$000000+%0111 ; Settle Time ; DC VIDEO+$0A0000+%0110 ; Integrate ; DC VIDEO+$010000+%0111 ; Settling time = 400 nsec ; DC VIDEO+$010000+%0011 ; Start A/D convert ; DC VIDEO+$180000+%0111 ; Hold A/D input at least 400 ns ; DC VIDEO+$180000+%0111 ; Hold A/D input at least 400 ns ; DC CLK3+0000+FSYNC+F1+F2 ; DC VIDEO+$0F0000+%0111 ; Settling time ;END_RD_COLS_NOXFER ZERO_BIASES DC END_ZERO_BIASES-ZERO_BIASES-1 DC (CLK2<<8)+(0<<14)+CLK_ZERO DC (CLK2<<8)+(2<<14)+CLK_ZERO DC (CLK2<<8)+(4<<14)+CLK_ZERO DC (CLK2<<8)+(6<<14)+CLK_ZERO DC (CLK2<<8)+(8<<14)+CLK_ZERO DC (CLK2<<8)+(10<<14)+CLK_ZERO DC (CLK2<<8)+(12<<14)+CLK_ZERO DC (CLK2<<8)+(14<<14)+CLK_ZERO DC (CLK2<<8)+(16<<14)+CLK_ZERO DC (CLK2<<8)+(18<<14)+CLK_ZERO DC (CLK2<<8)+(20<<14)+CLK_ZERO DC (CLK2<<8)+(22<<14)+CLK_ZERO DC (CLK2<<8)+(24<<14)+CLK_ZERO DC (CLK2<<8)+(26<<14)+CLK_ZERO DC (CLK2<<8)+(28<<14)+CLK_ZERO DC (CLK2<<8)+(30<<14)+CLK_ZERO DC (CLK2<<8)+(32<<14)+CLK_ZERO DC (CLK2<<8)+(34<<14)+CLK_ZERO DC (CLK2<<8)+(36<<14)+CLK_ZERO DC (CLK2<<8)+(38<<14)+CLK_ZERO DC (CLK2<<8)+(40<<14)+CLK_ZERO DC (CLK2<<8)+(42<<14)+CLK_ZERO DC (CLK2<<8)+(44<<14)+CLK_ZERO DC (CLK2<<8)+(46<<14)+CLK_ZERO END_ZERO_BIASES ; Initialize all DACs, starting with the clock driver ones CLOCKS DC END_CLOCKS-CLOCKS-1 ; Clocking voltages DC (CLK2<<8)+(0<<14)+@CVI(CLK_ZERO) ; Pin #1 N/C DC (CLK2<<8)+(1<<14)+@CVI(CLK_ZERO) DC (CLK2<<8)+(2<<14)+@CVI(CLK_ZERO) ; Pin #2 N/C DC (CLK2<<8)+(3<<14)+@CVI(CLK_ZERO) DC (CLK2<<8)+(4<<14)+@CVI(CLK_HI) ; Pin #3 VROWON DC (CLK2<<8)+(5<<14)+@CVI(CLK_LO) DC (CLK2<<8)+(6<<14)+@CVI(VDDCL_CLK) ; Pin #4 VDDCL DC (CLK2<<8)+(7<<14)+@CVI(VDDCL_CLK) DC (CLK2<<8)+(8<<14)+@CVI(CLK_HI) ; Pin #5 RDES DC (CLK2<<8)+(9<<14)+@CVI(CLK_LO) DC (CLK2<<8)+(10<<14)+@CVI(CLK_HI) ; Pin #6 VRSTOFF DC (CLK2<<8)+(11<<14)+@CVI(CLK_LO) DC (CLK2<<8)+(12<<14)+@CVI(CLK_HI) ; Pin #7 VRSTR DC (CLK2<<8)+(13<<14)+@CVI(CLK_LO) DC (CLK2<<8)+(14<<14)+@CVI(VGGCL_CLK) ; Pin #8 VGGCL DC (CLK2<<8)+(15<<14)+@CVI(VGGCL_CLK) DC (CLK2<<8)+(16<<14)+@CVI(CLK_HI) ; Pin #9 SSYNC DC (CLK2<<8)+(17<<14)+@CVI(CLK_LO) DC (CLK2<<8)+(18<<14)+@CVI(CLK_HI) ; Pin #10 S1 DC (CLK2<<8)+(19<<14)+@CVI(CLK_LO) DC (CLK2<<8)+(20<<14)+@CVI(CLK_HI) ; Pin #11 S2 DC (CLK2<<8)+(21<<14)+@CVI(CLK_LO) DC (CLK2<<8)+(22<<14)+@CVI(CLK_HI) ; Pin #12 SOE DC (CLK2<<8)+(23<<14)+@CVI(CLK_LO) ; Clocking voltages for the top half of the board DC (CLK2<<8)+(24<<14)+@CVI(CLK_HI) ; Pin #13 FSYNC DC (CLK2<<8)+(25<<14)+@CVI(CLK_LO) DC (CLK2<<8)+(26<<14)+@CVI(CLK_HI) ; Pin #14 F1 DC (CLK2<<8)+(27<<14)+@CVI(CLK_LO) DC (CLK2<<8)+(28<<14)+@CVI(CLK_HI) ; Pin #15 F2 DC (CLK2<<8)+(29<<14)+@CVI(CLK_LO) DC (CLK2<<8)+(30<<14)+@CVI(CLK_ZERO) ; Pin #16 N/C DC (CLK2<<8)+(31<<14)+@CVI(CLK_ZERO) DC (CLK2<<8)+(32<<14)+@CVI(CLK_ZERO) ; Pin #17 N/C DC (CLK2<<8)+(33<<14)+@CVI(CLK_ZERO) DC (CLK2<<8)+(34<<14)+@CVI(CLK_ZERO) ; Pin #18 N/C DC (CLK2<<8)+(35<<14)+@CVI(CLK_ZERO) DC (CLK2<<8)+(36<<14)+@CVI(CLK_ZERO) ; Pin #19 N/C DC (CLK2<<8)+(37<<14)+@CVI(CLK_ZERO) DC (CLK2<<8)+(38<<14)+@CVI(VNROW_CLK) ; Pin #33 N/C DC (CLK2<<8)+(39<<14)+@CVI(VNROW_CLK) DC (CLK2<<8)+(40<<14)+@CVI(VNCOL_CLK) ; Pin #34 N/C DC (CLK2<<8)+(41<<14)+@CVI(VNCOL_CLK) DC (CLK2<<8)+(42<<14)+@CVI(CLK_ZERO) ; Pin #35 N/C DC (CLK2<<8)+(43<<14)+@CVI(CLK_ZERO) DC (CLK2<<8)+(44<<14)+@CVI(CLK_ZERO) ; Pin #36 N/C DC (CLK2<<8)+(45<<14)+@CVI(CLK_ZERO) DC (CLK2<<8)+(46<<14)+@CVI(CLK_ZERO) ; Pin #37 N/C DC (CLK2<<8)+(47<<14)+@CVI(CLK_ZERO) END_CLOCKS ; DC Bias voltages assignments for the two first video boardss #0 and #1. BIASES DC END_BIASES-BIASES-1 ; Video board #0, wired for 5 volt operation = default ; Bipolar -5 to +5 volts supplies DC $0c4000+@CVI((VDETCOM+5.0)/10.0*4095) ; Pin #1 Vdetcom DC $0c8000+@CVI((VDDUC+5.0)/10.0*4095) ; Pin #2 VddUC DC $0cc000+@CVI((VDDOUT+5.0)/10.0*4095) ; Pin #3 VDDOut ; Bipolar +5 to -5 volt supplies DC $0d0000+@CVI((IREF+5.0)/10.0*4095) ; Pin #4 Iref DC $0d4000+@CVI((VSSCOM+5.0)/10.0*4095) ; Pin #5 VSSCom DC $0d8000+@CVI((VROWOFF+5.0)/10.0*4095) ; Pin #6 VRowOff DC $0dc000+@CVI(BIAS_SOURCE) ; Pin #7 N/C ; Video board #1, wired for 5 volt operation = default DC $1c4000+@CVI(BIAS_ZERO) ; Pin #1 N/C DC $1c8000+@CVI(BIAS_ZERO) ; Pin #2 N/C DC $1cc000+@CVI((VDDOUT+5.0)/10.0*4095) ; Pin #3 VDDOut DC $1d0000+@CVI(BIAS_ZERO) ; Pin #4 N/C DC $1d4000+@CVI((VP_T+5.0)/10.0*4095) ; Pin #5 VP_T DC $1d8000++@CVI((VTEND+5.0)/10.0*4095) ; Pin #6 VT_END DC $1dc000+@CVI(BIAS_SOURCE) ; Pin #7 N/C ; Video board #0, wired for 5 volt operation = default ; Bipolar -5 to +5 volts supplies DC $2c4000+@CVI((VDETCOM+5.0)/10.0*4095) ; Pin #1 Vdetcom DC $2c8000+@CVI((VDDUC+5.0)/10.0*4095) ; Pin #2 VddUC DC $2cc000+@CVI((VDDOUT+5.0)/10.0*4095) ; Pin #3 VDDOut ; Bipolar +5 to -5 volt supplies DC $2d0000+@CVI((IREF+5.0)/10.0*4095) ; Pin #4 Iref DC $2d4000+@CVI((VSSCOM+5.0)/10.0*4095) ; Pin #5 VSSCom DC $2d8000+@CVI((VROWOFF+5.0)/10.0*4095) ; Pin #6 VRowOff DC $2dc000+@CVI(BIAS_SOURCE) ; Pin #7 N/C ; Video board #1, wired for 5 volt operation = default DC $3c4000+@CVI(BIAS_ZERO) ; Pin #1 N/C DC $3c8000+@CVI(BIAS_ZERO) ; Pin #2 N/C DC $3cc000+@CVI((VDDOUT+5.0)/10.0*4095) ; Pin #3 VDDOut DC $3d0000+@CVI(BIAS_ZERO) ; Pin #4 N/C DC $3d4000+@CVI((VP_T+5.0)/10.0*4095) ; Pin #5 VP_T DC $3d8000++@CVI((VTEND+5.0)/10.0*4095) ; Pin #6 VT_END DC $3dc000+@CVI(BIAS_SOURCE) ; Pin #7 N/C ; Set bit #2 to generate a reset FIFO = RSTFIFO* low for 500 nsec ; Integrator gain ; DC $0c3001 ; Integrate 1, R = 4k, Low gain, Slow ; DC $0c3005 ; Also reset the FIFO DC $0c0000+@CVI((ADREF+5)/10.0*4095) DC $1c0000+@CVI((ADREF+5)/10.0*4095) DC $2c0000+@CVI((ADREF+5)/10.0*4095) DC $3c0000+@CVI((ADREF+5)/10.0*4095) DC $0c3000 ; Integrate 1, Reset FIFO DC $1c3000 ; Integrate 1, Reset FIFO DC $2c3000 ; Integrate 1, Reset FIFO DC $3c3000 ; Integrate 1, Reset FIFO ; DAC settings for the video offsets with four video boards installed DC $0e0000+OFFSETA ; Output #0 - Board #0 DC $0e4000+OFFSETA ; Output #1 DC $0e8000+OFFSETA ; Output #2 DC $0ec000+OFFSETA ; Output #3 DC $0f0000+OFFSETA ; Output #4 DC $0f4000+OFFSETA ; Output #5 DC $0f8000+OFFSETA ; Output #6 DC $0fc000+OFFSETA ; Output #7 DC $1e0000+OFFSETB ; Output #0 - Board #1 DC $1e4000+OFFSETB ; Output #1 DC $1e8000+OFFSETB ; Output #2 DC $1ec000+OFFSETB ; Output #3 DC $1f0000+OFFSETB ; Output #4 DC $1f4000+OFFSETB ; Output #5 DC $1f8000+OFFSETB ; Output #6 DC $1fc000+OFFSETB ; Output #7 DC $2e0000+OFFSETC ; Output #0 - Board #2 DC $2e4000+OFFSETC ; Output #1 DC $2e8000+OFFSETC ; Output #2 DC $2ec000+OFFSETC ; Output #3 DC $2f0000+OFFSETC ; Output #4 DC $2f4000+OFFSETC ; Output #5 DC $2f8000+OFFSETC ; Output #6 DC $2fc000+OFFSETC ; Output #7 DC $3e0000+OFFSETD ; Output #0 - Board #3 DC $3e4000+OFFSETD ; Output #1 DC $3e8000+OFFSETD ; Output #2 DC $3ec000+OFFSETD ; Output #3 DC $3f0000+OFFSETD ; Output #4 DC $3f4000+OFFSETD ; Output #5 DC $3f8000+OFFSETD ; Output #6 DC $3fc000+OFFSETD ; Output #7 END_BIASES START_UP DC END_START_UP-START_UP-1 DC $1d0000+@CVI((VNROW+7.5)/7.5*4095) ; Pin #4 VnRow DC $1d4000+@CVI((VNCOL+7.5)/7.5*4095) ; Pin #5 VnCol END_START_UP END_WAVEFORMS