Nov/Dec 2005 Engineering Run

This engineering run took place over Nov 29 - Dec 3 at the Perkins Telescope, with Mimir operational and on the telescope. This was the first engineering run devoted to improved detector operations and improvement of data collection efficiency.

Present for the run were Dan Clemens and Brian Taylor, with consulting from Marc Buie.

We used the first half of nights, staring around 3pm and turning the telescope and instrument over to observers around 11-midnight.

Areas and issues addressed included:

1. Detector Operations
   1. Removal of the "ski jumps" at the top and bottom of each image
      • The cause of the ski jumps proved to be multiple: between images, we had been running an "idle" routine that cycled through the detector's row clocks. Originally, this idle mode also included the "row-by-row" reset commands, but these were later droped. Nevertheless, we found that turning off the row clocking in idle mode made a significant improvement in the ski jump problem.
      • Second, as part of working on the "global reset" timing and voltages, we found that excessively long delays between the release of the global reset and the initiation of the first readout also contributed to generating ski jumps in the images. Although the hot pixel problem (see below) is reduced by having longer resting periods after the reset release (ie, longer than 100 microseconds), the ski jump begins to grow if the resting period exceeds 40 microseconds.
      • So, to reduce (but still not fully cure) the ski jumps, we removed row clocking in idle and reduced the global reset resting time (charge sloshing time) to 40 microseconds. In this configuration, the ski jumps are limited to 3-4 rows at the top and bottom of the images
      • Interestingly, the ski jumps are NOT thermal in origin. Short darks (reset-read-read) and long darks (reset-read-integrate-read) show identical ski jumps.
   2. Reduce hot pixels in long images
      • We started by varying the VRSTG high and low voltages, finding that the widest voltage swing yielded the lowest number of hot pixels
      • We next varied the global reset pulse duration and found essentially no change from 1 microsec to 100 microsec. We elected to use a 4 microsecond pulse for all remaining tests.
      • The big change came when we varied the time delay between release of the global reset line and the initiation of the first read. If the time was too short, there were lots and lots of hot pixels. As we lengthened the delay, the hot pixels decreased strongly, more strongly than for any variation in the VRSTG voltage values. The number of hot pixels dropped below 1% for a 30 sec dark once the delay was at least 40 microseconds and improved only slowly with longer delay times. We attribute this delay effect to charge sloshing in the infrared sensing InSb, though why it should be so long is odd.
      • We initially set the delay to 170 microseconds, but later reduced it to 40 microseconds to contain the ski jump growth introduced by the long delay times.
   3. Well Depth Improvement
      • Well depths for the May/June 2005 run were quite shallow, as low as 20,000 electrons for some rows in the lower half of the array, though up to 3-4 times more in the upper half.
      • Well depth depends on VBIAS, which is the difference between VDDUC and VDETCOM. We had been operating with VBIAS apparently set to -0.625V, which should have been "deeper" than the -0.4V Raytheon found was optimal. However, when we tried reducing VBIAS to -0.4V the chip stopped seeing light altogether! Instead, we stepped VBIAS up through -1.0V finding deeper wells at least through -0.9V. Brian speculates that with the manganin ribbon cable connecting to the detector, we may be seeing significant voltage drops on the lines that pull current. VDDUC is one of those, so its actual value at the chip may be less than at the Leach electronics. If so, then the failure at VBIAS = -0.4V might tell us the size of the voltage drop. We set the "apparent" VBIAS to -0.85V, believing this might correspond to an "actual" VBIAS ~ -0.45V, and have achieved quite good results:
        • The big difference in sensitivity we had been seeing between the top half and bottom half of the array is gone
        • The odd-even row differences are much reduced
        • The chip cosmetically looks much better and more uniformly responsive
        • The apparent well depth is about 8,000 counts. If the conversion gain remains 10 e/ADU, this implies 80,000 electrons well depth, which is probably not too awful. The deepest Raytheon advertises is about 300,000.
   4. Lost, Mis-Located Columns (Kokepeli to the rescue...)
      • In some runs, we found some quadrants had scrambled their column order so that some central columns were shifted to the outer edge of the image. An entire IDL package ("kokepeli analysis") was built to find and fix this problem in software after the fact.
      • In changing the DC offsets for each quadrant to put the RAW1 ADC values in the upper part of their ranges (> 30,000 counts), we inadvertently introduced column order problems.
        • If the offset values were more than $7F0, the column order was compromised
        • Below $7F0 the images were sky-true
      • The DC offsets are generated by DACs on the A/D board and feed directly into op-amps in the video chains. We can see no reason why changing these voltages introduces what amounts to a timing error in the column clocks. We will continue to investigate..
   5. Faster Reads by reduced pixel read times
      • At present, the time to read, digitize, and store one pixel is 7.48 microseconds. This is significantly longer than we had hoped. There are four main sources of dwell/delay that produce this time, some of which are interleaved (pipelined) by processing two pixels through the video chain together:
        • The rise time of the pixel analog data. We have found through experimentation (and by reading the Raytheon manual very carefully) that it takes up to 5 microseconds for the analog data from a pixel to reach stability. During that time, the pixel output voltage is slowly rising and if the pixel read times are short compared to 5 microseconds, some of one pixel's analog signal ends up added to the next read by that amplifier, producing a "ghost" echo 8 columns later in time (ie closer to the image center).
        • The integration time used to integrate the pixel analog signal on an integrate-and-hold circuit before presentation to the ADC. This integration time sets the electronic gain of the system, in the sense that longer integrations give more gain (fewer electons per ADU). At present, that time is set to 1.0 microseconds.
        • The conversion time of the ADC, which is at least 2 microseconds
        • The burst time of the 32 channels of ADC data off the 4 A/D boards and out the fiber to the control computer. This time amounts to about 3 clock ticks (of 40 ns each) per channel, for a total of 3.88 microseconds. We found that if we shortened this, that excess noise was generated in the image.
        • By interlacing the rise time and integration time of one pixel with the ADC conversion of a previous pixel and holding all quiet during data bursts, we achieve the lowest read noise and best image quality. But, this mode gives the relatively long 7.48 microseconds per pixel.
      • We experimented by removing 3 microseconds from the burst dwell time. This raised the image noise, but only by about a factor of 3. This increase is below the photon noise of half-filled wells, making this faster read option attractive for L and M band imaging.
      • To shorten the pixel read time more, or to achieve short read times without raising the image noise, some suppression of buss or voltage noise must occur. We will consult with Bob Leach about this.
   6. RAW1 instability improved
   • The mean ADUs in the first reads of a CDS image were found to jump around alot during the May/June run, but not as much in other runs. We experimented this fall in changing VRSTG voltages to try to achieve better RAW1 stability and had some success.
   • After tuning the VRSTG pulse width and delay and removing the row clock cycling during idle, the RAW1 instability seems much improved.
   • Interestingly, we can induce *more* stability by changing the quadrant offset voltages and will seek an understanding to this effect.
   • We plan to test reducing the offset voltage and measuring the increase in RAW1 stability to find a good operating point that still yields adequate well depth "headroom".
   7. Still to try:
   1. Column clamping during row transitions, using VDDCL and VGGCL
   2. Boosting VIREF to see if the 5 microsecond pixel rise time can be shortened
   3. Varying VDDOUT to see if rise time or well depth can be improved