| Welcome Message |
| Curriculum Vitae |
| Research Interests |
| Academic Background |
| Skills |
| Work Experience |
| List of Publications |
| Honors and Awards |
| Activities |
| Contact |
 Md. Ashfaquzzaman Khan |
Working on tools and methodologies for front-end design automation of digital circuits.
Research Assistant, Boston University, MA (September 2008 - June 2012):
Worked towards PhD under the supervision of Prof. Martin C. Herbordt. Focused on acceleration of bio-medical applications, e.g. Molecular Dynamics Simulation and its discrete version, using advanced systems like FPGAs, GPUs, and Multi-core processors. Also studied energy/temperature aspects of parallel applications in general. Actively took part in graduate level course preparation/instruction and preparation of research proposals.
Intern, Intel Corporation, Hudson, MA (May 2011 - October 2011):
Enabled UPF (Unified Power Format, an industry standard) based power aware front end design flow, especially for next generation CPUs. Specific works included the following. 1. Proposing a UPF based design methodology to work seamlessly with the existing design flow and to ensure smooth transition. 2. Converting power specification from XML based Intel internal format to UPF based description. 3. Developing a library of Tcl procedures to reduce the verbosity of native UPF without sacrificing readability. 4. Establishing a backward compatible conversion path from UPF to XML, to support other Intel internal tools. 5. Validating the new methods and the converted design. 6. Developing documentation and training materials.
Intern, Microsoft Research, Redmond, WA (May 2010 - July 2010):
Developed gNOSIS, a board-level debugging and verification tool for FPGA designs. gNOSIS uses the Capture/Readback features of the FPGA to checkpoint the entire state of the circuit with little or no modification to the DUT. It then correlates the design registers provided in the netlist with their state in the FPGA configuration memory, and with the expected state. If the states match, execution proceeds by restoring the state of the FPGA and continuing execution for a set number of cycles. When an error is encountered, the time and location of the error is reported and the last good checkpoint is used for further debugging. gNOSIS eliminates the manual labor and long wait times required by currently available tools (e.g. Chipscope), and provides greater visibility at a lower cost.
Engineer, Sony Corporation, Japan (April 2006 - August 2008)
Developed a system level simulator for Cell Broadband Engine Architecture (CBEA).
Written in SystemC, this simulator could provide cycle information for a
given benchmark circuit, when it would run on CBEA, with 95% accuracy. The
simulator ran a few hundred times faster than Cell SDK and thus provided a
quick way to evaluate different architectural parameters, e.g. memory
bandwidth. I also made an extended version of the simulator, which could
handle up to 128 SPEs (Synergistic Processing Elements).
Developed Noise Reduction Application for Sony digital camera, Cybershot series (Market arrival time: 2009).
Summer Intern, Panasonic, Japan (August 2003 - September 2003)
Verified scripts that were written to accelerate system level design of digital circuits.
Part-time Programmer at DataFair Limited, Japan (February 2002 - March 2006)
Developed business software for wholesale product suppliers using Visual Basic 6, MS-SQL and MS-ACCESS.