Md. Ashfaquzzaman Khan
CAD Engineer, Intel Corporation, Folsom, CA (Since July, 2012)
PhD, Computer Engineering, Boston University, 2013 (Defense: June 2012)

CONTACT

E-mail: azkhan at_bu_dot_edu
Phone: 1-917-496-2699 (Mobile)
Homepage: http://people.bu.edu/azkhan

RESEARCH INTERESTS

Computer Architecture and Multicore/Reconfigurable/Embedded Systems
High-performance Computing and Acceleration of Bio-medical Applications
CAD/EDA Tools and Simulation Technologies

EDUCATION

PhD, Computer Engineering, September 2008 - January 2013 (Defense: June, 2012)
Dept. of Electrical and Computer Engineering, Boston University, Boston, MA
Advisor: Prof. Martin C. Herbordt
Dissertation Title (Nominated for Best Dissertation Award): "Scalable Molecular Dynamics Simulation using FPGAs and Multicore Processors"
GPA: 3.88/4.0 (Ranked 1st in the ECE PhD Qualifying Exam 2009)

Master of Eng, Electronic Engineering, April 2004 - March 2006
Graduate School of Engineering, Tohoku University, Sendai, Japan
Thesis Title: "A Study on Time-multiplexing of Reconfigurable LSI"
GPA: 3.93/4.0

Bachelor of Eng, Electronic Engineering, April 2000 - March 2004
Faculty of Engineering, Tohoku University, Sendai, Japan
GPA: 3.88/4.0, Major GPA: 3.92/4.0 (Ranked 1st in the class)

PROFESSIONAL EXPERIENCE

CAD Engineer, Intel Corporation, Folsom, CA (July 2012 - Present):
Working on tools and methodologies for front-end design automation of digital circuits, with special focus on High-Level Synthesis (HLS).

Research Assistant, Boston University, MA (September 2008 - June 2012):
Worked towards PhD under the supervision of Prof. Martin C. Herbordt. Focused on acceleration of bio-medical applications, e.g. Molecular Dynamics Simulation and its discrete version, using advanced systems like FPGAs, GPUs, and Multi-core processors. Also studied energy/temperature aspects of parallel applications in general. Actively took part in graduate level course preparation/instruction and preparation of research proposals.

Intern, Intel Corporation, Hudson, MA (May 2011 - October 2011):
Enabled UPF (Unified Power Format, an industry standard) based power aware front end design flow, especially for next generation CPUs. Specific works included the following. 1. Proposing a UPF based design methodology to work seamlessly with the existing design flow and to ensure smooth transition. 2. Converting power specification from XML based Intel internal format to UPF based description. 3. Developing a library of Tcl procedures to reduce the verbosity of native UPF without sacrificing readability. 4. Establishing a backward compatible conversion path from UPF to XML, to support other Intel internal tools. 5. Validating the new methods and the converted design. 6. Developing documentation and training materials.

Intern, Microsoft Research, Redmond, WA (May 2010 - July 2010):
Developed gNOSIS, a board-level debugging and verification tool for FPGA designs. gNOSIS uses the Capture/Readback features of the FPGA to checkpoint the entire state of the circuit with little or no modification to the DUT. It then correlates the design registers provided in the netlist with their state in the FPGA configuration memory, and with the expected state. If the states match, execution proceeds by restoring the state of the FPGA and continuing execution for a set number of cycles. When an error is encountered, the time and location of the error is reported and the last good checkpoint is used for further debugging. gNOSIS eliminates the manual labor and long wait times required by currently available tools (e.g. Chipscope), and provides greater visibility at a lower cost.

Engineer, Sony Corporation, Japan (April 2006 - August 2008):
Developed a system level simulator for Cell Broadband Engine Architecture (CBEA). Written in SystemC, this simulator can provide cycle information for a given benchmark circuit, when it will run on CBEA, with 95% accuracy. The simulator runs a few hundred times faster than Cell SDK and thus provides a quick way to evaluate different architectural parameters. I also made an extended version of the simulator, which can handle up to 128 SPEs (Synergistic Processing Elements).

Developed Noise Reduction Application for Sony digital camera, Cybershot series (Market arrival time: 2009).

Summer Intern, Panasonic, Japan (August 2003 - September 2003):
Verified scripts that were written to accelerate system level design of digital circuits.

Part-time Programmer at DataFair Limited, Japan (February 2002 - March 2006):
Developed business software for wholesale product suppliers using Visual Basic 6, MS-SQL and MS-ACCESS.

COMPUTER SKILLS

Platforms: Linux/Unix, Windows

Software Development Environments: Eclipse, MS Visual Studio, Emacs
Software Programming Languages:
C, C++, Assembly
Perl, Tcl
HTML, JavaScript, PHP, MySQL, Visual Basic, MS-SQL
Others: Ruby, Java, MATLAB

Hardware Description/Programming Languages: Verilog/System Verilog, VHDL, SystemC
CAD/EDA Tools: Cadence CtoS, Virtuoso Layout Editor, Dracula DRC; Synopsys Design Compiler, NanoSim, CosmosScope, VCS NLP; Mentor Graphics Modelsim; Springsoft Verdi
FPGA IDEs: Xilinx ISE, Altera Quartus

Others: Pthread, Openmp, VTune, Perf, Pfmon, Cuda

PATENT AND PUBLICATIONS (Selected)

PATENT
Md. Ashfaquzzaman Khan, Yasushi Fukuda, "Data Processing Apparatus, Method Therefor, And Computer Program", Pending Application No. 12/487799, Filed 2009, USA (Original: Pending Application No. P2008-161516, Filed 2008, Japan)

BOOK CHAPTER
Md. Ashfaquzzaman Khan, Matt Chiu, Martin C. Herbordt, "FPGA-Accelerated Molecular Dynamics", In Wim Vanderbauwhede, Khaled Benkrid, "High-Performance Computing using FPGAs", Springer 2013 (Accepted)

JOURNAL/CONFERENCE
Md. Ashfaquzzaman Khan, Martin C. Herbordt, "Communication Requirements for FPGA-Centric Molecular Dynamics", Symposium on Application Accelerators in High-Performance Computing (SAAHPC) 2012

Md. Ashfaquzzaman Khan, Martin C. Herbordt, "Parallel Discrete Molecular Dynamics Simulation with Speculation and In-Order Commitment", Journal of Computational Physics (JCP) 2011, 230 (17): 6563-6582

Md. Ashfaquzzaman Khan, Can Hankendi, Ayse Kivilcim Coskun, Martin C. Herbordt, "Application Level Optimizations for Energy Efficiency and Thermal Stability", Annual Workshop on High Performance Embedded Computing (HPEC) 2011

Md. Ashfaquzzaman Khan, Can Hankendi, Ayse Kivilcim Coskun, Martin C. Herbordt, "Software Optimization for Performance, Energy, and Thermal Distribution: Initial Case Studies", International Green Computing Conference and Workshops (IGCC) 2011, pp 1-6

Matt Chiu, Md. Ashfaquzzaman Khan, Martin C. Herbordt, "Efficient Calculation of Pairwise Nonbonded Forces", International Symposium on Field-Programmable Custom Computing Machines (FCCM) 2011, pp 73-76

Md. Ashfaquzzaman Khan, Richard Neil Pittman, Alessandro Forin, "gNOSIS: A Board-level Debugging and Verification Tool", International Conference on ReConFigurable Computing and FPGAs (ReConFig) 2010, pp 43-48

Martin C. Herbordt, Md. Ashfaquzzaman Khan, Tony Dean, "Parallel Discrete Event Simulation of Molecular Dynamics Through Event-Based Decomposition", International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2009, pp 129-136

Bharat Sukhwani, Matt Chiu, Md. Ashfaquzzaman Khan, Martin C. Herbordt, "Effective Floating Point Applications on FPGAs: Examples from Molecular Modeling", Annual Workshop on High Performance Embedded Computing (HPEC) 2009

Martin C. Herbordt, Bharat Sukhwani, Matt Chiu, Md. Ashfaquzzaman Khan, "Production Floating Point Applications on FPGAs", Symposium on Application Accelerators in High Performance Computing (SAAHPC) 2009

Roel Pantonial, Md. Ashfaquzzaman Khan, Naoto Miyamoto, Koji Kotani, Shigetoshi Sugawa, Tadahiro Ohmi, "Improving Execution Speed of FPGA using Dynamically Reconfigurable Technique", Asia and South Pacific Design Automation Conference (ASP-DAC) 2007, pp 108-109 [Received Special Feature Award]

Md. Ashfaquzzaman Khan, Naoto Miyamoto, Roel Pantonial, Koji Kotani, Shigetoshi Sugawa, Tadahiro Ohmi, "Improving Multi-Context Execution Speed on DRFPGAs", Asian Solid-State Circuits Conference (A-SSCC) 2006, pp 275-278

Md. Ashfaquzzaman Khan, Naoto Miyamoto, Takeshi Ohkawa, Amir Jamak, Soichiro Kita, Koji Kotani, Tadahiro Ohmi, "An Aproach to Realize Time-sharing of Flip-Flops in Time-multiplexed FPGAs", International Conference on Field Programmable Technology (ICFPT) 2004, pp 351-354

DISSERTATION/THESIS
Doctoral Dissertation, Boston University, 2013 (Defense: June 2012): "Scalable Molecular Dynamics Simulation using FPGAs and Multicore Processors"

Master's Thesis, Tohoku University, 2006: "A Study on Time-multiplexing of Reconfigurable LSI"

AWARDS AND HONORS (Selected)

Ranked 1st in the ECE PhD Qualifying Exam:
April 2009, Department of Electrical & Computer Engineering, Boston University, Boston, MA.

Dean's Fellowship Award 2008:
Awarded by the Dean of the College of Engineering, Boston University. The award included tuition for PhD course and monthly stipend.

ASP-DAC 2007 Special Feature Award:
Awarded at the University LSI Design Contest of the ASP-DAC 2007, in recognition of the design and implementation of FP3, a dynamically reconfigurable LSI. I developed this LSI as a part of my master's research work.

Outstanding Research Award 2006:
Awarded by the Electrical & Information Eng. Managing Board, Graduate School of Engineering, Tohoku University, in recognition of excellent research for master's thesis.

Tohoku University President's Award 2004:
Awarded by the President of Tohoku University, in recognition of excellent undergraduate academic performance. I topped the merit list of the Department of Electronic Engineering.

Monbukagakusho Scholarship 1999-2006:
Awarded by the Ministry of Education, Culture, Sports, Science and Technology, Japan. I received it for two terms, 1999-2004 and 2004-2006, for a total of seven years. The scholarship provided full tuition fee and a monthly stipend for undergraduate and master's studies in Japan.

Certificate of Excellence 1997:
Awarded by the Adjutant General of Bangladesh Army in recognition of excellent performance in Higher Secondary Certificate (H.S.C.) examination. (H.S.C. is the countrywide final exam for high school students of Bangladesh.) I topped the merit list in my region. I also became the 2nd top ranked student in the entire country.

Bangladesh Prime Minister's Award 1995:
Awarded by the Prime Minister of the People's Republic of Bangladesh for ranking in the merit list (top 20) in the Secondary School Certificate (S.S.C.) examination.

Others:
Dean's Award 2004, IEICE Encouragement Prize 2004 etc.

PROFESSIONAL ACTIVITIES (REVIEWS)

HEART (Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies): 2012

DAC (Design Automation Conference): 2012

SASP (Symposium on Application Specific Processors): 2011

JEST (Journal of Electronic Science and Technology): 2011

FCCM (International Symposium on Field-Programmable Custom Computing Machines): 2011, 2010

PARCO (Journal of Parallel Computing): 2010

LSPP (Large-Scale Parallel Processing Workshop): 2010

PDS (Parallel and Distributed Systems): 2009