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Published conference papers
A. Smirnov, A. Taubin, Synthesizing Asynchronous Micropipelines with Design Compiler, Proc.
SNUG Boston 2006: Synopsys User Group, September 18-19, 2006 [pdf]
A. Smirnov, A. Taubin, M. Su, and M. G. Karpovsky, An Automated
Fine-Grain Pipelining Using Domino Style Asynchronous Library, Proc.
ACSD 2005 : Fifth International Conference on Application of Concurrency to
System Design [pdf]
K. Kulikowski, M. Su, A. Smirnov, A. Taubin, and M. G.
Karpovsky, D. MacDonald, "Delay Insensitive Encoding and Power Analysis: A
Balancing Act", Proc. 11th Int. Symp. on Asynchronous Circuits and Systems,
2005 [pdf]
M. A. Penya, J. Cortadella, E. Pastor, A. B. Smirnov "A case
study for the verification of complex timed circuits: IPCMOS." DATE'2002,
Paris, March, 2002 [pdf]
N. A. Starodoubtsev, M. V. Goncharov, I. V. Klotchkov, A.
B. Smirnov. Towards synthesis of monotonic asynchronous circuits from Signal
Transition Graphs. International Conference on Application of Concurrency to
System Design 2001 [pdf ]
M. V. Goncharov, A. B. Smirnov, I. V. Klotchkov, N. A.
Starodoubtsev STG Timing Extensions and Simulation. VHDL users forum Santa
Clara, California, USA, March 1998 [pdf]
M. V. Goncharov, I. V. Klotchkov, A. B. Smirnov, N. A.
Starodoubtsev Timing extensions of STG model and a method to simulate
timed STG behavior in VHDL environment. International Conference on Application
of Concurrency to System Design. Aizu, Japon, March 1998 [pdf]
Workshop presentations
K. Kulikowski, A. Smirnov, A. Taubin. "Automated Design of Cryptographic Devices
Resistant to Multiple Side-Channel Attacks" in Workshop on Cryptographic Hardware
and Embedded Systems (CHES) October 10-13, 2006 Yokohama, Japan [to appear]
A. Smirnov, M. Karpovsky, A. Taubin. "On Automatic Synthesis of Data Dependent Micropipelines"
in IWLS 2006 Fifteenth International Workshop on Logic and Synthesis. June 7-9,
2006. Vail, Colorado, USA
Smirnov A., Taubin A., Karpovsky M. and Rozenblyum L. Gate Transfer Level
Synthesis as an Automated Approach to Fine-Grain Pipelining. in Workshop on
Token Based Computing (ToBaCo). June 22, 2004. Bologna, Italy [pdf]
Smirnov A., Taubin A., and Karpovsky M. Automated Pipelining in
ASIC Synthesis Methodology: Gate Transfer Level. in IWLS 2004 Thirteenth
International Workshop on Logic and Synthesis. June 2-4, 2004. Temecula,
California, USA [pdf]
A. B. Smirnov, N. A. Starodoubtsev, I. V. Klotchkov, M.
V. Goncharov. A Technique to Automate STG Analysis and Refinement for CSC and
Normalcy. PATMOS, Yverdon, Switzerland, September 2001 [pdf]
A. B. Smirnov, M. V. Goncharov, I. V. Klotchkov, N. A. Starodoubtsev. A
Technique to Automate STG Analysis and Refinement for CSC and Normalcy. First
ACiD-WG workshop of the European Commission's Fifth Framework Programme.
Neuchatel, Switzerland, February 2001.
N. A. Starodoubtsev, M. V. Goncharov, I. V. Klotchkov, A.
B. Smirnov. Synthesis of asynchronous interface circuits by STG refinement.
International Workshop on Asynchronous INTerfaces. TU Delft, Netherlands,
September 2000 [pdf]
N. A. Starodoubtsev, M. V. Goncharov, I. V. Klotchkov, A.
B. Smirnov. STG Refinement for Synthesis of Negative Gate Circuits. Third
ACiD-WG Workshop. Newcastle upon Tyne, UK, January 1999.
I. V. Klotchkov, A. B. Smirnov, N. A. Starodoubtsev
Verification driven synthesis of asynchronous circuits from STG specification.
International Workshop - Power and Timing Modeling, Optimization and
Simulation. Lyngby, Danmark, October 1998 [pdf]
A. B. Smirnov, I. V. Klotchkov Algorithms for
analysis and synthesis based on partial states. Special Interest Workshop on
Exploitation of STG-based Design Technology. St Petersburg, Russia, June 1998.
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